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127 Commits

Author SHA1 Message Date
David Harris
34880771af Fixed IROM coverage issues in IFU 2023-05-01 08:32:52 -07:00
David Harris
c1786bfec8 IMMU exclude non word-sized accesses 2023-05-01 08:14:19 -07:00
David Harris
d5c350c597 Merged coverage exclusions for PMP 2023-04-28 08:04:25 -07:00
David Harris
ca5a71bbe5 PMA Checker coverage 2023-04-28 07:53:59 -07:00
Liam
6803347a49 Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
David Harris
e43de9c194
Merge pull request #282 from ross144/main 
Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
 2023-04-27 07:23:10 -07:00
David Harris
0ad5165795
Merge pull request #283 from SydRiley/main 
Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
 2023-04-26 15:40:01 -07:00
Sydeny
a40cc17dc7 For ifu and lsu exclusions added missing row numbers 2023-04-26 15:30:22 -07:00
Ross Thompson
e72fa0c081 Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data. 2023-04-26 17:29:57 -05:00
Sydeny
efcb59ee35 Exclusion in the ifu and lsu to increase coverage, added missing row numbers 2023-04-26 15:26:39 -07:00
Sydeny
25b69a47a1 Excluding untoggled signals in ifu and lsu, ifu coverage from 83.68% to 84.06% and lsu from 93.45% to 93.58% 2023-04-26 14:37:55 -07:00
Sydeny
069ca0ec29 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-26 03:00:25 -07:00
Sydeny
f5258d3b22 added comments to exclusions 2023-04-26 03:00:13 -07:00
Alec Vercruysse
6299c0ef0b Cacheway Exclude FlushStage=1 when SetValidWay=1 
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
 2023-04-25 20:30:46 -07:00
Alec Vercruysse
9f417ee93d extend invalidatecache d$ exclusion to statement coverage 2023-04-25 17:00:13 -07:00
Diego Herrera Vicioso
c681789296 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
David Harris
8be5ed9b67 Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
Ross Thompson
ffa686a605
Merge pull request #264 from davidharrishmc/dev 
Added -fp flag to run arch64d/f tests in coverage
 2023-04-20 09:26:16 -05:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
039a06ec95 clarifying comments in exclusions 2023-04-19 14:47:34 -07:00
Sydeny
b76ed145e6 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
David Harris
a3f3967f59 Added -fp flag to run arch64d/f tests in coverage 2023-04-19 13:07:07 -07:00
Alec Vercruysse
b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
e3593800d9 fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Sydeny
f0ff1a4447 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 2023-04-17 14:19:48 -07:00
David Harris
b00b8ba366 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
David Harris
cfca584bc7 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
2e568877b0 fdivsqrtfsm coverage attempt to waive a state 2023-04-13 17:40:14 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
Limnanthes Serafini
1125bad9cb
Merge branch 'openhwgroup:main' into cachesim 2023-04-13 16:54:35 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Sydeny
1dab409bae Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
a52eb01407 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
92cd0cb6ab track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
Alec Vercruysse
a3d9e11b0f cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
James E. Stine
dee4d49e42 Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
e303d99d5b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
Limnanthes Serafini
e6269b364f Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
3b6e397172 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
978b475269 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
729f81a0df refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
James Stine
5d1ad53bc7 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
Limnanthes Serafini
3f7f3d6a42 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
David Harris
baef1249e7 Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now 2023-04-10 07:05:06 -07:00
eroom1966
430763a1d1 add support into configuration for Zb(a,b,c,s) 2023-04-06 16:30:14 +01:00