From f4d778c2f633f6f089397f6d27d641809067745a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 19 Dec 2021 15:10:33 -0600 Subject: [PATCH] Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. --- wally-pipelined/src/lsu/lsu.sv | 4 ++-- wally-pipelined/src/mmu/hptw.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 09c1f28c..65772a71 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -222,8 +222,8 @@ module lsu // signal to CPU it needs to wait on HPTW. assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | - (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) | - (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS); + (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) | + (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); // When replaying CPU memory request after PTW select the IEUAdrM for correct address. assign SelReplayCPURequest = NextState == STATE_T0_READY; diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv index cb520788..d2a5fa1a 100644 --- a/wally-pipelined/src/mmu/hptw.sv +++ b/wally-pipelined/src/mmu/hptw.sv @@ -199,7 +199,7 @@ module hptw // LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF; // else NextWalkerState = FAULT; LEAF: if (DTLBWalk) NextWalkerState = IDLE; // updates TLB - else NextWalkerState = LEAF_DELAY; + else NextWalkerState = IDLE; LEAF_DELAY: NextWalkerState = IDLE; // give time to allow address translation FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT; else NextWalkerState = IDLE;