forked from Github_Repos/cvw
Page table walker now walks the table.
Added interlock so the icache stalls. Page table walker not walking correctly, goes to fault state.
This commit is contained in:
Ross Thompson
parent
bc9c944ba0
commit
dd84f2958e
@ -33,11 +33,11 @@ add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -89,6 +89,7 @@ add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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@ -104,7 +105,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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@ -117,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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@ -174,41 +175,45 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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@ -237,15 +242,17 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/HRDATAW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemAckW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/StallW
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
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@ -297,16 +304,48 @@ add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/M
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/CurrentPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
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add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
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add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
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add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
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add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
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add wave -noupdate -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
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add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
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add wave -noupdate /testbench/dut/hart/lsu/DataStall
|
||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/ExtIntM
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HSELUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HADDR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWRITE
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWDATA
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESPUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADYUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/SIN
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DSRb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DCDb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/CTSb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/RIb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/pendingPGrouped
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/intPending
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/nextIntPending
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/requests
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/GPIOIntr
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/UARTIntr
|
||||
add wave -noupdate /testbench/dut/uncore/genblk4/uart/u/intrpending
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {11172098 ns} 0} {{Cursor 3} {7672141 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
WaveRestoreCursors {{Cursor 5} {9729816 ns} 0} {{Cursor 6} {7857655 ns} 0} {{Cursor 7} {7869135 ns} 1} {{Cursor 8} {7868621 ns} 0} {{Cursor 9} {7868621 ns} 0} {{Cursor 10} {7865190 ns} 0} {{Cursor 11} {7867237 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 189
|
||||
configure wave -justifyvalue left
|
||||
@ -321,4 +360,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {11171939 ns} {11172253 ns}
|
||||
WaveRestoreZoom {9729788 ns} {9730412 ns}
|
||||
|
||||
21
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
21
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
@ -40,8 +40,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
|
||||
input logic [31:0] ICacheMemReadData,
|
||||
input logic ICacheMemReadValid,
|
||||
// The address at which we want to search the cache memory
|
||||
output logic [`PA_BITS-1:0] PCTagF,
|
||||
output logic [`PA_BITS-1:0] PCNextIndexF,
|
||||
output logic [`PA_BITS-1:0] PCTagF,
|
||||
output logic [`PA_BITS-1:0] PCNextIndexF,
|
||||
output logic ICacheReadEn,
|
||||
// Load data into the cache
|
||||
output logic ICacheMemWriteEnable,
|
||||
@ -56,13 +56,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
|
||||
|
||||
// Outputs to pipeline control stuff
|
||||
output logic ICacheStallF, EndFetchState,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
|
||||
// Signals to/from ahblite interface
|
||||
// A read containing the requested data
|
||||
input logic [`XLEN-1:0] InstrInF,
|
||||
input logic InstrAckF,
|
||||
// The read we request from main memory
|
||||
output logic [`PA_BITS-1:0] InstrPAdrF,
|
||||
output logic [`PA_BITS-1:0] InstrPAdrF,
|
||||
output logic InstrReadF
|
||||
);
|
||||
|
||||
@ -109,6 +111,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
|
||||
|
||||
|
||||
localparam STATE_INVALIDATE = 18; // *** not sure if invalidate or evict? invalidate by cache block or address?
|
||||
localparam STATE_TLB_MISS = 19;
|
||||
|
||||
|
||||
localparam AHBByteLength = `XLEN / 8;
|
||||
localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
|
||||
@ -209,7 +213,9 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
|
||||
STATE_READY: begin
|
||||
PCMux = 2'b00;
|
||||
ICacheReadEn = 1'b1;
|
||||
if (hit & ~spill) begin
|
||||
if (ITLBMissF) begin
|
||||
NextState = STATE_TLB_MISS;
|
||||
end else if (hit & ~spill) begin
|
||||
SavePC = 1'b1;
|
||||
ICacheStallF = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
@ -363,6 +369,13 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
|
||||
ICacheStallF = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
STATE_TLB_MISS: begin
|
||||
if (ITLBWriteF) begin
|
||||
NextState = STATE_READY;
|
||||
end else begin
|
||||
NextState = STATE_TLB_MISS;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
PCMux = 2'b01;
|
||||
NextState = STATE_READY;
|
||||
|
||||
21
wally-pipelined/src/cache/icache.sv
vendored
21
wally-pipelined/src/cache/icache.sv
vendored
@ -28,24 +28,27 @@
|
||||
module icache
|
||||
(
|
||||
// Basic pipeline stuff
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD,
|
||||
input logic FlushD,
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD,
|
||||
input logic FlushD,
|
||||
input logic [`PA_BITS-1:0] PCNextF,
|
||||
input logic [`PA_BITS-1:0] PCPF,
|
||||
// Data read in from the ebu unit
|
||||
input logic [`XLEN-1:0] InstrInF,
|
||||
input logic InstrAckF,
|
||||
input logic [`XLEN-1:0] InstrInF,
|
||||
input logic InstrAckF,
|
||||
// Read requested from the ebu unit
|
||||
output logic [`PA_BITS-1:0] InstrPAdrF,
|
||||
output logic InstrReadF,
|
||||
output logic InstrReadF,
|
||||
// High if the instruction currently in the fetch stage is compressed
|
||||
output logic CompressedF,
|
||||
output logic CompressedF,
|
||||
// High if the icache is requesting a stall
|
||||
output logic ICacheStallF,
|
||||
output logic ICacheStallF,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
|
||||
// The raw (not decompressed) instruction that was requested
|
||||
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
|
||||
output logic [31:0] FinalInstrRawF
|
||||
output logic [31:0] FinalInstrRawF
|
||||
);
|
||||
|
||||
// Configuration parameters
|
||||
|
||||
@ -51,6 +51,7 @@ module ahblite (
|
||||
input logic MemReadM, MemWriteM,
|
||||
input logic [`XLEN-1:0] WriteDataM,
|
||||
input logic [1:0] MemSizeM,
|
||||
//output logic DataStall,
|
||||
// Signals from MMU
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
input logic MMUStall,
|
||||
@ -158,10 +159,10 @@ module ahblite (
|
||||
// *** Ross Thompson remove this datastall
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
|
||||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
|
||||
MMUStall);
|
||||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
|
||||
//assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
|
||||
// MMUStall);
|
||||
|
||||
|
||||
@ -86,6 +86,7 @@ module lsuArb
|
||||
|
||||
logic [1:0] CurrState, NextState;
|
||||
logic SelPTW;
|
||||
logic HPTWStallD;
|
||||
|
||||
|
||||
flopr #(2) StateReg(
|
||||
@ -140,7 +141,12 @@ module lsuArb
|
||||
// *** need to rename DcacheStall and Datastall.
|
||||
// not clear at all. I think it should be LSUStall from the LSU,
|
||||
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
||||
assign HPTWStall = SelPTW ? DataStall : 1'b1;
|
||||
assign HPTWStallD = SelPTW ? DataStall : 1'b1;
|
||||
flopr #(1) HPTWStallReg (.clk(clk),
|
||||
.reset(reset),
|
||||
.d(HPTWStallD),
|
||||
.q(HPTWStall));
|
||||
|
||||
assign DCacheStall = SelPTW ? 1'b0 : DataStall; // *** this is probably going to change.
|
||||
|
||||
endmodule
|
||||
|
||||
@ -164,7 +164,7 @@ module pagetablewalker (
|
||||
|
||||
flopenl #(3) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
|
||||
assign PRegEn = (WalkerState == LEVEL1 || WalkerState == LEVEL0) && ~HPTWStall;
|
||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
|
||||
|
||||
// State transition logic
|
||||
always_comb begin
|
||||
@ -184,13 +184,11 @@ module pagetablewalker (
|
||||
else NextWalkerState = FAULT;
|
||||
LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV;
|
||||
else NextWalkerState = LEVEL0;
|
||||
LEVEL0: if (ValidPTE && LeafPTE && ~AccessAlert)
|
||||
LEVEL0: if (ValidPTE & LeafPTE & ~AccessAlert)
|
||||
NextWalkerState = LEAF;
|
||||
else NextWalkerState = FAULT;
|
||||
LEAF: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
FAULT: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
LEAF: NextWalkerState = IDLE;
|
||||
FAULT: NextWalkerState = IDLE;
|
||||
// Default case should never happen, but is included for linter.
|
||||
default: NextWalkerState = IDLE;
|
||||
endcase
|
||||
@ -278,8 +276,8 @@ module pagetablewalker (
|
||||
|
||||
flopenl #(4) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
|
||||
assign PRegEn = (WalkerState == LEVEL1 || WalkerState == LEVEL0 ||
|
||||
WalkerState == LEVEL2 || WalkerState == LEVEL3) && ~HPTWStall;
|
||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
||||
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
|
||||
|
||||
always_comb begin
|
||||
case (WalkerState)
|
||||
@ -329,13 +327,9 @@ module pagetablewalker (
|
||||
if (ValidPTE && LeafPTE && ~AccessAlert) NextWalkerState = LEAF;
|
||||
else NextWalkerState = FAULT;
|
||||
|
||||
LEAF: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
LEAF: NextWalkerState = IDLE;
|
||||
|
||||
FAULT: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
FAULT: NextWalkerState = IDLE;
|
||||
// Default case should never happen, but is included for linter.
|
||||
default: NextWalkerState = IDLE;
|
||||
endcase
|
||||
|
||||
@ -250,6 +250,7 @@ module wallypipelinedhart
|
||||
.HPTWReady(HPTWReadyfromLSU),
|
||||
.Funct3MfromLSU(Funct3MfromLSU),
|
||||
.StallWfromLSU(StallWfromLSU),
|
||||
// .DataStall(LSUStall),
|
||||
.* ); // data cache unit
|
||||
|
||||
ahblite ebu(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user