From dd84f2958e1c32b8e0a2cef380bcf4be95a00c72 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Tue, 29 Jun 2021 22:33:57 -0500
Subject: [PATCH] Page table walker now walks the table. Added interlock so the
icache stalls. Page table walker not walking correctly, goes to fault state.
---
wally-pipelined/regression/wave.do | 181 +++++++++++-------
wally-pipelined/src/cache/ICacheCntrl.sv | 21 +-
wally-pipelined/src/cache/icache.sv | 21 +-
wally-pipelined/src/ebu/ahblite.sv | 5 +-
wally-pipelined/src/lsu/lsuArb.sv | 8 +-
wally-pipelined/src/mmu/pagetablewalker.sv | 22 +--
.../src/wally/wallypipelinedhart.sv | 1 +
7 files changed, 158 insertions(+), 101 deletions(-)
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index a051f071..78d6f1a6 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -33,11 +33,11 @@ add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@@ -89,6 +89,7 @@ add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
+add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
@@ -104,7 +105,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
@@ -117,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
-add wave -noupdate -expand -group alu -divider internals
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu -divider internals
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
@@ -174,41 +175,45 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
-add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
-add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
-add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
-add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
-add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
-add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
-add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
-add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
-add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
-add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
-add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
-add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
-add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
-add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
-add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
+add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
+add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
+add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
+add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
+add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
+add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
+add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
+add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
+add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
+add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
+add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
+add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
+add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
+add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
+add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA
+add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked
+add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext
add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState
add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
@@ -237,15 +242,17 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/CurrState
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/DataStall
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemAdrM
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemPAdrM
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataW
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/HRDATAW
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemAckW
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/StallW
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
@@ -297,16 +304,48 @@ add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/M
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/CurrentPTE
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
-add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
-add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
-add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
-add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
-add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
-add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
+add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
+add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
+add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
+add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
+add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
+add wave -noupdate -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
+add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
add wave -noupdate /testbench/dut/hart/lsu/DataStall
+add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/ExtIntM
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HSELUART
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HADDR
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWRITE
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWDATA
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADUART
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESPUART
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADYUART
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/SIN
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DSRb
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DCDb
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/CTSb
+add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/RIb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/SOUT
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RTSb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/DTRb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT1b
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT2b
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/pendingPGrouped
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/intPending
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/nextIntPending
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/requests
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/GPIOIntr
+add wave -noupdate /testbench/dut/uncore/genblk2/plic/UARTIntr
+add wave -noupdate /testbench/dut/uncore/genblk4/uart/u/intrpending
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {11172098 ns} 0} {{Cursor 3} {7672141 ns} 0}
-quietly wave cursor active 2
+WaveRestoreCursors {{Cursor 5} {9729816 ns} 0} {{Cursor 6} {7857655 ns} 0} {{Cursor 7} {7869135 ns} 1} {{Cursor 8} {7868621 ns} 0} {{Cursor 9} {7868621 ns} 0} {{Cursor 10} {7865190 ns} 0} {{Cursor 11} {7867237 ns} 0}
+quietly wave cursor active 1
configure wave -namecolwidth 250
configure wave -valuecolwidth 189
configure wave -justifyvalue left
@@ -321,4 +360,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {11171939 ns} {11172253 ns}
+WaveRestoreZoom {9729788 ns} {9730412 ns}
diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv
index f290f0ad..78bdb46a 100644
--- a/wally-pipelined/src/cache/ICacheCntrl.sv
+++ b/wally-pipelined/src/cache/ICacheCntrl.sv
@@ -40,8 +40,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
input logic [31:0] ICacheMemReadData,
input logic ICacheMemReadValid,
// The address at which we want to search the cache memory
- output logic [`PA_BITS-1:0] PCTagF,
- output logic [`PA_BITS-1:0] PCNextIndexF,
+ output logic [`PA_BITS-1:0] PCTagF,
+ output logic [`PA_BITS-1:0] PCNextIndexF,
output logic ICacheReadEn,
// Load data into the cache
output logic ICacheMemWriteEnable,
@@ -56,13 +56,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// Outputs to pipeline control stuff
output logic ICacheStallF, EndFetchState,
+ input logic ITLBMissF,
+ input logic ITLBWriteF,
// Signals to/from ahblite interface
// A read containing the requested data
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
// The read we request from main memory
- output logic [`PA_BITS-1:0] InstrPAdrF,
+ output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF
);
@@ -109,6 +111,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
localparam STATE_INVALIDATE = 18; // *** not sure if invalidate or evict? invalidate by cache block or address?
+ localparam STATE_TLB_MISS = 19;
+
localparam AHBByteLength = `XLEN / 8;
localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
@@ -209,7 +213,9 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
STATE_READY: begin
PCMux = 2'b00;
ICacheReadEn = 1'b1;
- if (hit & ~spill) begin
+ if (ITLBMissF) begin
+ NextState = STATE_TLB_MISS;
+ end else if (hit & ~spill) begin
SavePC = 1'b1;
ICacheStallF = 1'b0;
NextState = STATE_READY;
@@ -363,6 +369,13 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
ICacheStallF = 1'b0;
NextState = STATE_READY;
end
+ STATE_TLB_MISS: begin
+ if (ITLBWriteF) begin
+ NextState = STATE_READY;
+ end else begin
+ NextState = STATE_TLB_MISS;
+ end
+ end
default: begin
PCMux = 2'b01;
NextState = STATE_READY;
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index abf828fc..89b2ff9e 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -28,24 +28,27 @@
module icache
(
// Basic pipeline stuff
- input logic clk, reset,
- input logic StallF, StallD,
- input logic FlushD,
+ input logic clk, reset,
+ input logic StallF, StallD,
+ input logic FlushD,
input logic [`PA_BITS-1:0] PCNextF,
input logic [`PA_BITS-1:0] PCPF,
// Data read in from the ebu unit
- input logic [`XLEN-1:0] InstrInF,
- input logic InstrAckF,
+ input logic [`XLEN-1:0] InstrInF,
+ input logic InstrAckF,
// Read requested from the ebu unit
output logic [`PA_BITS-1:0] InstrPAdrF,
- output logic InstrReadF,
+ output logic InstrReadF,
// High if the instruction currently in the fetch stage is compressed
- output logic CompressedF,
+ output logic CompressedF,
// High if the icache is requesting a stall
- output logic ICacheStallF,
+ output logic ICacheStallF,
+ input logic ITLBMissF,
+ input logic ITLBWriteF,
+
// The raw (not decompressed) instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
- output logic [31:0] FinalInstrRawF
+ output logic [31:0] FinalInstrRawF
);
// Configuration parameters
diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 39cc70d2..735590e1 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -51,6 +51,7 @@ module ahblite (
input logic MemReadM, MemWriteM,
input logic [`XLEN-1:0] WriteDataM,
input logic [1:0] MemSizeM,
+ //output logic DataStall,
// Signals from MMU
/* -----\/----- EXCLUDED -----\/-----
input logic MMUStall,
@@ -158,9 +159,9 @@ module ahblite (
// *** Ross Thompson remove this datastall
/* -----\/----- EXCLUDED -----\/-----
assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
- (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
- MMUStall);
+ (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE));
-----/\----- EXCLUDED -----/\----- */
+
//assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
// MMUStall);
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index d7e62782..0d26af4c 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -86,6 +86,7 @@ module lsuArb
logic [1:0] CurrState, NextState;
logic SelPTW;
+ logic HPTWStallD;
flopr #(2) StateReg(
@@ -140,7 +141,12 @@ module lsuArb
// *** need to rename DcacheStall and Datastall.
// not clear at all. I think it should be LSUStall from the LSU,
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
- assign HPTWStall = SelPTW ? DataStall : 1'b1;
+ assign HPTWStallD = SelPTW ? DataStall : 1'b1;
+ flopr #(1) HPTWStallReg (.clk(clk),
+ .reset(reset),
+ .d(HPTWStallD),
+ .q(HPTWStall));
+
assign DCacheStall = SelPTW ? 1'b0 : DataStall; // *** this is probably going to change.
endmodule
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index eecd46f1..5bc15df3 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -164,7 +164,7 @@ module pagetablewalker (
flopenl #(3) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
- assign PRegEn = (WalkerState == LEVEL1 || WalkerState == LEVEL0) && ~HPTWStall;
+ assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
// State transition logic
always_comb begin
@@ -184,13 +184,11 @@ module pagetablewalker (
else NextWalkerState = FAULT;
LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV;
else NextWalkerState = LEVEL0;
- LEVEL0: if (ValidPTE && LeafPTE && ~AccessAlert)
+ LEVEL0: if (ValidPTE & LeafPTE & ~AccessAlert)
NextWalkerState = LEAF;
else NextWalkerState = FAULT;
- LEAF: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
- else NextWalkerState = IDLE;
- FAULT: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
- else NextWalkerState = IDLE;
+ LEAF: NextWalkerState = IDLE;
+ FAULT: NextWalkerState = IDLE;
// Default case should never happen, but is included for linter.
default: NextWalkerState = IDLE;
endcase
@@ -278,8 +276,8 @@ module pagetablewalker (
flopenl #(4) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
- assign PRegEn = (WalkerState == LEVEL1 || WalkerState == LEVEL0 ||
- WalkerState == LEVEL2 || WalkerState == LEVEL3) && ~HPTWStall;
+ assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
+ WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
always_comb begin
case (WalkerState)
@@ -329,13 +327,9 @@ module pagetablewalker (
if (ValidPTE && LeafPTE && ~AccessAlert) NextWalkerState = LEAF;
else NextWalkerState = FAULT;
- LEAF: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
- else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
- else NextWalkerState = IDLE;
+ LEAF: NextWalkerState = IDLE;
- FAULT: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
- else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
- else NextWalkerState = IDLE;
+ FAULT: NextWalkerState = IDLE;
// Default case should never happen, but is included for linter.
default: NextWalkerState = IDLE;
endcase
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 28b8ccde..e23fd511 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -250,6 +250,7 @@ module wallypipelinedhart
.HPTWReady(HPTWReadyfromLSU),
.Funct3MfromLSU(Funct3MfromLSU),
.StallWfromLSU(StallWfromLSU),
+// .DataStall(LSUStall),
.* ); // data cache unit
ahblite ebu(