Merge branch 'main' of https://github.com/kipmacsaigoren/cvw

README.md

@@ -5,7 +5,7 @@ Wally is a 5-stage pipelined processor configurable to support all the standard
 
 ![Wally block diagram](wallyriscvTopAll.png)
 
-Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
+Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
 
 # New User Setup
 

pipelined/src/generic/mem/ram1p1rwbe.sv

@@ -69,6 +69,26 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
 
+  end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
+     genvar index;
+     // 64 x 128-bit SRAM
+     logic [WIDTH-1:0] BitWriteMask;
+     for (index=0; index < WIDTH; index++) 
+       assign BitWriteMask[index] = bwe[index/8];
+    TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+			      .A(addr), .D(din), 
+			      .BWEB(~BitWriteMask), .Q(dout));
+     
+  end else if (`USE_SRAM == 1 && WIDTH == 22  && DEPTH == 32) begin
+     genvar index;
+     // 64 x 22-bit SRAM
+     logic [WIDTH-1:0] BitWriteMask;
+     for (index=0; index < WIDTH; index++) 
+       assign BitWriteMask[index] = bwe[index/8];
+     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+			      .A(addr), .D(din), 
+			      .BWEB(~BitWriteMask), .Q(dout));     
+    
   // ***************************************************************************
   // READ first SRAM model
   // ***************************************************************************

pipelined/src/generic/mem/ram1p1rwbe_64x22.sv

@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// ram1p1rwbe_64x22.sv
+//
+// Written: james.stine@okstate.edu 2 Feburary 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram1p1rwbe_64x22( 
+  input  logic          CLK, 
+  input  logic 	        CEB, 
+  input  logic          WEB,
+  input  logic [5:0]    A, 
+  input  logic [127:0]  D,
+  input  logic [127:0]  BWEB, 
+  output logic [127:0]  Q
+);
+
+   // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor
+   generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+
+endmodule

pipelined/src/generic/mem/ram2p1r1wbe.sv

@@ -64,6 +64,18 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 				  .QA(rd1),
 				  .QB());
 
+   end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
+   
+      ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
+				  .CEBA(~ce1), .CEBB(~ce2),
+				  .WEBA('0), .WEBB(~we2),			      
+				  .AA(ra1), .AB(wa2),
+				  .DA('0),
+				  .DB(wd2),
+				  .BWEBA('0), .BWEBB('1),
+				  .QA(rd1),
+				  .QB());      
+
    end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
 
       logic [SRAMWIDTH-1:0]     SRAMReadData;      

pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv

@@ -0,0 +1,48 @@
+///////////////////////////////////////////
+// ram2p1rwbe_1024x36.sv
+//
+// Written: james.stine@okstate.edu 2 February 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram2p1r1wbe_1024x36( 
+  input  logic          CLKA, 
+  input  logic          CLKB, 
+  input  logic 	        CEBA, 
+  input  logic 	        CEBB, 
+  input  logic          WEBA,
+  input  logic          WEBB,
+  input  logic [9:0]    AA, 
+  input  logic [9:0]    AB, 
+  input  logic [35:0]   DA,
+  input  logic [35:0]   DB,
+  input  logic [35:0]   BWEBA, 
+  input  logic [35:0]   BWEBB, 
+  output logic [35:0]   QA,
+  output logic [35:0]   QB
+);
+
+   // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor
+   generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+   			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+
+endmodule

pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv

@@ -41,7 +41,7 @@ module ram2p1r1wbe_1024x68(
   output logic [67:0]   QB
 );
 
-   // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
+   // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor
    generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
 			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
 

pipelined/src/generic/mem/rom1p1r.sv

@@ -38,9 +38,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
 
    // Core Memory
    logic [DATA_WIDTH-1:0] 	 ROM [(2**ADDR_WIDTH)-1:0];
-   if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin
+   if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin
       rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
 
+   end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin
+      rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));      
+
    end else begin
       always @ (posedge clk) begin
 	 if(ce) dout <= ROM[addr];    

pipelined/src/hazard/hazard.sv

@@ -68,7 +68,7 @@ module hazard (
   assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE;
   assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE));
   assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
-  assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM);
+  assign FlushWCause = TrapM;
 
   // Stall causes
   //  Most data depenency stalls are identified in the decode stage

pipelined/src/ifu/bpred/bpred.sv

@@ -116,7 +116,7 @@ module bpred (
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
     speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
@@ -149,6 +149,7 @@ module bpred (
           .PredValidF,
           .PredictionInstrClassWrongE,
           .IEUAdrE,
+          .InstrClassD,
           .InstrClassE);
 
   // the branch predictor needs a compact decoding of the instruction class.
@@ -179,12 +180,14 @@ module bpred (
 	assign PredInstrClassF = InstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
 						PredInstrClassF[2] |
-						(PredInstrClassF[1]) ;
+						PredInstrClassF[1] |
+						PredInstrClassF[3];
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
 						PredInstrClassF[2] |
-						(PredInstrClassF[1] & PredValidF) ;
+						(PredInstrClassF[1] & PredValidF) |
+						(PredInstrClassF[3] & PredValidF);
   end
   
   // Part 3 RAS

pipelined/src/ifu/bpred/btb.sv

@@ -41,6 +41,7 @@ module btb #(parameter int Depth = 10 ) (
   // update
   input  logic             PredictionInstrClassWrongE,             // BTB's instruction class guess was wrong
   input  logic [`XLEN-1:0] IEUAdrE,                                // Branch/jump target address to insert into btb
+  input  logic [3:0]       InstrClassD,                            // Instruction class to insert into btb
   input  logic [3:0]       InstrClassE                             // Instruction class to insert into btb
 );
 
@@ -49,12 +50,12 @@ module btb #(parameter int Depth = 10 ) (
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
   logic [`XLEN-1:0] 		ResetPC;
   logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
-  logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [`XLEN+4:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
   logic [`XLEN+3:0] 		TableBTBPredictionF;
   logic [`XLEN-1:0] 		PredPCD;  
   logic [3:0] 				PredInstrClassD;  // *** copy of reg outside module
   logic 					UpdateEn;
-  logic 					TablePredValidF;
+  logic 					TablePredValidF, PredValidD;
     
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
@@ -78,13 +79,13 @@ module btb #(parameter int Depth = 10 ) (
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
-  assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
+  assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} :
-                                MatchD ? {PredInstrClassD, PredPCD} :
+                                MatchD ? {PredValidD, InstrClassD, PredPCD} :
-                                {InstrClassE, IEUAdrE} ;
+                                {1'b1, InstrClassE, IEUAdrE} ;
 
-  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
+  flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
-  assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
+  assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF};
 
   always_ff @ (posedge clk) begin
     if (reset) begin
@@ -95,7 +96,7 @@ module btb #(parameter int Depth = 10 ) (
 	if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
   end
 
-  assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
+  //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
   
   assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
 
@@ -104,6 +105,6 @@ module btb #(parameter int Depth = 10 ) (
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
-  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
+  flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD});
 
 endmodule

pipelined/src/ifu/bpred/speculativegshare.sv

@@ -36,7 +36,7 @@ module speculativegshare #(parameter int k = 10 ) (
   output logic [1:0] 	  DirPredictionF, 
   output logic 			  DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
   input logic [3:0] 	  PredInstrClassF, InstrClassD, InstrClassE,
   input logic [3:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE