From 8a6eaa23cc3fbb1db56a5df3f8ca73a98dba1d13 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 22:03:51 -0600 Subject: [PATCH 1/8] Minor optimization to btb. --- pipelined/src/ifu/bpred/bpred.sv | 1 + pipelined/src/ifu/bpred/btb.sv | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 048aa112..9889607a 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -149,6 +149,7 @@ module bpred ( .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, + .InstrClassD, .InstrClassE); // the branch predictor needs a compact decoding of the instruction class. diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index 02c77fab..dc32d914 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -41,6 +41,7 @@ module btb #(parameter int Depth = 10 ) ( // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassE // Instruction class to insert into btb ); @@ -71,7 +72,7 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex; + assign MatchF = PCNextFIndex == PCFIndex & PredValidF; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; @@ -79,7 +80,7 @@ module btb #(parameter int Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {PredInstrClassD, PredPCD} : + MatchD ? {InstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); @@ -104,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); endmodule From c3e3afe39885adb8c0572943ebda09e8af7ffbda Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 00:24:54 -0600 Subject: [PATCH 2/8] Minor change to btb. --- pipelined/src/ifu/bpred/btb.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index dc32d914..7cf9ed99 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -50,12 +50,12 @@ module btb #(parameter int Depth = 10 ) ( logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; - logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; - logic TablePredValidF; + logic TablePredValidF, PredValidD; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -72,20 +72,20 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex & PredValidF; + assign MatchF = PCNextFIndex == PCFIndex; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {InstrClassD, PredPCD} : - {InstrClassE, IEUAdrE} ; + assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : + MatchD ? {PredValidD, InstrClassD, PredPCD} : + {1'b1, InstrClassE, IEUAdrE} ; - flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; always_ff @ (posedge clk) begin if (reset) begin @@ -96,7 +96,7 @@ module btb #(parameter int Depth = 10 ) ( if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end - assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; + //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; @@ -105,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); endmodule From 2a5b6408f26504f4d23cf8548e8f6f617ec3eca9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:27:58 -0600 Subject: [PATCH 3/8] Removed unused signal. --- pipelined/src/ifu/bpred/bpred.sv | 2 +- pipelined/src/ifu/bpred/speculativegshare.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 9889607a..c72e9014 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -116,7 +116,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 23a49eac..1eb888a9 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -36,7 +36,7 @@ module speculativegshare #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE From 0035579553e182de25a51bdbf195ce58f5f5e105 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:59:38 -0600 Subject: [PATCH 4/8] Minor branch predictor bug fix. --- pipelined/src/ifu/bpred/bpred.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index c72e9014..66414965 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -180,12 +180,14 @@ module bpred ( assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[2] | - (PredInstrClassF[1]) ; + PredInstrClassF[1] | + PredInstrClassF[3]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) ; + (PredInstrClassF[1] & PredValidF) | + (PredInstrClassF[3] & PredValidF); end // Part 3 RAS From 230888db8be70349eeb6c655e6fc84acc1235141 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 2 Feb 2023 08:52:06 -0600 Subject: [PATCH 5/8] Fixed bug #47 discovered by Lee Moore. ECALL and EBREAK do not commit their results. --- pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 9dd3c0e4..650e8367 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -68,7 +68,7 @@ module hazard ( assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE; assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; - assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM); + assign FlushWCause = TrapM; // Stall causes // Most data depenency stalls are identified in the decode stage From b66177fd87700391753d19ed7ed2464a8ee04463 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 2 Feb 2023 13:28:18 -0600 Subject: [PATCH 6/8] Modify generic/mem for rv32gc ram2 --- pipelined/src/generic/mem/ram2p1r1wbe.sv | 12 +++++ .../src/generic/mem/ram2p1r1wbe_1024x36.sv | 48 +++++++++++++++++++ .../src/generic/mem/ram2p1r1wbe_1024x68.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 5 +- 4 files changed, 65 insertions(+), 2 deletions(-) create mode 100755 pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv index 3c93ce86..08c232bb 100644 --- a/pipelined/src/generic/mem/ram2p1r1wbe.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe.sv @@ -64,6 +64,18 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); + end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + + ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin logic [SRAMWIDTH-1:0] SRAMReadData; diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv new file mode 100755 index 00000000..0aad7db4 --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// ram2p1rwbe_1024x36.sv +// +// Written: james.stine@okstate.edu 2 February 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_1024x36( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [9:0] AA, + input logic [9:0] AB, + input logic [35:0] DA, + input logic [35:0] DB, + input logic [35:0] BWEBA, + input logic [35:0] BWEBB, + output logic [35:0] QA, + output logic [35:0] QB +); + + // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor + generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv index 11eacd5a..e6a6b625 100755 --- a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -41,7 +41,7 @@ module ram2p1r1wbe_1024x68( output logic [67:0] QB ); - // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor + // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 4669cadb..64cb9224 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -38,9 +38,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // Core Memory logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; - if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin + if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin + rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + end else begin always @ (posedge clk) begin if(ce) dout <= ROM[addr]; From bfa69ea2b3f496850efa6c43b98af7596278a5ce Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 2 Feb 2023 13:54:25 -0600 Subject: [PATCH 7/8] Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 --- pipelined/src/generic/mem/ram1p1rwbe.sv | 20 ++++++++++ pipelined/src/generic/mem/ram1p1rwbe_64x22.sv | 40 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100755 pipelined/src/generic/mem/ram1p1rwbe_64x22.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 028f928c..e33e708a 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -68,6 +68,26 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); + + end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin + genvar index; + // 64 x 128-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); + + end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin + genvar index; + // 64 x 22-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); // *************************************************************************** // READ first SRAM model diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv new file mode 100755 index 00000000..84c8d1b7 --- /dev/null +++ b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ram1p1rwbe_64x22.sv +// +// Written: james.stine@okstate.edu 2 Feburary 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram1p1rwbe_64x22( + input logic CLK, + input logic CEB, + input logic WEB, + input logic [5:0] A, + input logic [127:0] D, + input logic [127:0] BWEB, + output logic [127:0] Q +); + + // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor + generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + +endmodule From be618a0c341a1c7fee7fa92b2c0604b506f86b03 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 2 Feb 2023 12:59:28 -0800 Subject: [PATCH 8/8] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 12d7fe1f..1fec9286 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ Wally is a 5-stage pipelined processor configurable to support all the standard ![Wally block diagram](wallyriscvTopAll.png) -Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. +Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. # New User Setup