diff --git a/pipelined/src/muldiv/intdivrestoring.sv b/pipelined/src/muldiv/intdivrestoring.sv index b56bb477..b154809c 100644 --- a/pipelined/src/muldiv/intdivrestoring.sv +++ b/pipelined/src/muldiv/intdivrestoring.sv @@ -36,7 +36,7 @@ module intdivrestoring ( input logic clk, input logic reset, input logic StallM, - input logic TrapM, + input logic FlushE, input logic DivSignedE, W64E, input logic DivE, //input logic [`XLEN-1:0] SrcAE, SrcBE, @@ -122,7 +122,7 @@ module intdivrestoring ( ////////////////////////////// always_ff @(posedge clk) - if (reset | TrapM) begin + if (reset | FlushE) begin state <= IDLE; end else if (DivStartE) begin step <= 1; diff --git a/pipelined/src/muldiv/muldiv.sv b/pipelined/src/muldiv/muldiv.sv index d6bc26de..96d47173 100644 --- a/pipelined/src/muldiv/muldiv.sv +++ b/pipelined/src/muldiv/muldiv.sv @@ -42,7 +42,7 @@ module muldiv ( // Divide Done output logic DivBusyE, // hazards - input logic StallM, StallW, FlushM, FlushW, TrapM + input logic StallM, StallW, FlushE, FlushM, FlushW ); logic [`XLEN-1:0] MDUResultM; @@ -67,7 +67,7 @@ module muldiv ( end else begin assign DivE = MDUE & Funct3E[2]; assign DivSignedE = ~Funct3E[0]; - intdivrestoring div(.clk, .reset, .StallM, .TrapM, .DivSignedE, .W64E, .DivE, + intdivrestoring div(.clk, .reset, .StallM, .FlushE, .DivSignedE, .W64E, .DivE, .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM); end diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c61b5e1a..f2ff2a7e 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -375,7 +375,7 @@ module wallypipelinedcore ( .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, .MDUResultW, .DivBusyE, - .StallM, .StallW, .FlushM, .FlushW, .TrapM + .StallM, .StallW, .FlushE, .FlushM, .FlushW ); end else begin // no M instructions supported assign MDUResultW = 0;