forked from Github_Repos/cvw
424 lines
15 KiB
Systemverilog
424 lines
15 KiB
Systemverilog
///////////////////////////////////////////
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// wallypipelinedcore.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Pipelined RISC-V Processor
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_on UNUSED */
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module wallypipelinedcore (
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input logic clk, reset,
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// Privileged
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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// Bus Interface
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic [`XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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);
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// logic [1:0] ForwardAE, ForwardBE;
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic RetM;
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(* mark_debug = "true" *) logic TrapM;
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// new signals that must connect through DP
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logic MDUE, W64E;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic [1:0] AtomicM;
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logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM;
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logic [2:0] Funct3E;
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logic [31:0] InstrD;
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(* mark_debug = "true" *) logic [31:0] InstrM;
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logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
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logic [`XLEN-1:0] CSRReadValW, MDUResultW;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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(* mark_debug = "true" *) logic [1:0] MemRWM;
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(* mark_debug = "true" *) logic InstrValidM;
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logic InstrMisalignedFaultM;
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logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
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logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
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logic InvalidateICacheM, FlushDCacheM;
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logic PCSrcE;
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logic CSRWriteFenceM;
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logic DivBusyE;
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logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
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logic SquashSCW;
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// floating point unit signals
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logic [2:0] FRM_REGW;
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logic [4:0] RdM, RdW;
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logic FStallD;
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logic FWriteIntE;
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logic [`FLEN-1:0] FWriteDataM;
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logic [`XLEN-1:0] FIntResM;
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logic [`XLEN-1:0] FCvtIntResW;
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logic FCvtIntW;
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logic FDivBusyE;
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logic IllegalFPUInstrM;
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logic FRegWriteM;
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logic FCvtIntStallD;
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logic FpLoadStoreM;
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logic [1:0] FResSelW;
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logic [4:0] SetFflagsM;
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logic [`XLEN-1:0] FPIntDivResultW;
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// memory management unit signals
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logic ITLBWriteF;
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logic ITLBMissF;
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logic [`XLEN-1:0] SATP_REGW;
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logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
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logic [1:0] STATUS_MPP, STATUS_FS;
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logic [1:0] PrivilegeModeW;
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logic [`XLEN-1:0] PTE;
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logic [1:0] PageType;
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logic sfencevmaM, wfiM, IntPendingM;
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logic SelHPTW;
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// PMA checker signals
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var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
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// IMem stalls
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logic IFUStallF;
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logic LSUStallM;
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// cpu lsu interface
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] IEUAdrE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
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logic [`LLEN-1:0] ReadDataW;
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logic CommittedM;
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// AHB ifu interface
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logic [`PA_BITS-1:0] IFUHADDR;
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logic [2:0] IFUHBURST;
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logic [1:0] IFUHTRANS;
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logic [2:0] IFUHSIZE;
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logic IFUHWRITE;
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logic IFUHREADY;
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// AHB LSU interface
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logic [`PA_BITS-1:0] LSUHADDR;
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logic [`XLEN-1:0] LSUHWDATA;
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logic [`XLEN/8-1:0] LSUHWSTRB;
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logic LSUHWRITE;
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logic LSUHREADY;
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logic BPPredWrongE;
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logic BPPredDirWrongM;
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logic BTBPredPCWrongM;
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logic RASPredPCWrongM;
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logic BPPredClassNonCFIWrongM;
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logic [4:0] InstrClassM;
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logic InstrAccessFaultF, HPTWInstrAccessFaultM;
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logic [2:0] LSUHSIZE;
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logic [2:0] LSUHBURST;
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logic [1:0] LSUHTRANS;
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logic DCacheMiss;
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logic DCacheAccess;
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logic ICacheMiss;
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logic ICacheAccess;
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logic BreakpointFaultM, EcallFaultM;
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logic InstrDAPageFaultF;
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logic BigEndianM;
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logic FCvtIntE;
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logic CommittedF;
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ifu ifu(
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.clk, .reset,
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.StallF, .StallD, .StallE, .StallM,
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.FlushD, .FlushE, .FlushM, .FlushW,
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// Fetch
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.HRDATA, .PCF, .IFUHADDR,
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.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
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.IFUHREADY, .IFUHWRITE,
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.ICacheAccess, .ICacheMiss,
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// Execute
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.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
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.BPPredWrongE,
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// Mem
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.RetM, .TrapM, .CommittedF, .PrivilegedNextPCM, .InvalidateICacheM, .CSRWriteFenceM,
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.InstrD, .InstrM, .PCM, .InstrClassM, .BPPredDirWrongM,
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.BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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// Writeback
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// output logic
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// Faults
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.IllegalBaseInstrFaultD, .InstrPageFaultF,
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.IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
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// mmu management
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.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
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.STATUS_MPP, .ITLBWriteF, .sfencevmaM,
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.ITLBMissF,
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.InstrAccessFaultF,
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.InstrDAPageFaultF
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); // instruction fetch unit: PC, branch prediction, instruction cache
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ieu ieu(
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.clk, .reset,
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// Decode Stage interface
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.InstrD, .IllegalIEUInstrFaultD,
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.IllegalBaseInstrFaultD,
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// Execute Stage interface
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.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE,
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.IEUAdrE, .MDUE, .W64E,
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.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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// Memory stage interface
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.SquashSCW, // from LSU
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.MemRWM, // read/write control goes to LSU
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.AtomicM, // atomic control goes to LSU
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.WriteDataM, // Write data to LSU
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.Funct3M, // size and signedness to LSU
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.SrcAM, // to privilege and fpu
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.RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
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// Writeback stage
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.CSRReadValW, .MDUResultW, .FPIntDivResultW,
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.RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
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.InstrValidM,
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.FCvtIntResW,
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.FCvtIntW,
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// hazards
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.StallD, .StallE, .StallM, .StallW,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD,
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.PCSrcE,
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.CSRReadM, .CSRWriteM, .PrivilegedM,
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.CSRWriteFenceM, .StoreStallD
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); // integer execution unit: integer register file, datapath and controller
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lsu lsu(
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.clk, .reset, .StallM, .FlushM, .StallW,
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.FlushW(TrapM),
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// CPU interface
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.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
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.AtomicM,
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.SquashSCW,
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.FpLoadStoreM,
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.FWriteDataM,
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//.DataMisalignedM(DataMisalignedM),
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.IEUAdrE, .IEUAdrM, .WriteDataM,
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.ReadDataW, .FlushDCacheM,
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// connected to ahb (all stay the same)
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.LSUHADDR,
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.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS,
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.LSUHWRITE, .LSUHREADY,
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// connect to csr or privilege and stay the same.
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.PrivilegeModeW, .BigEndianM, // connects to csr
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.PMPCFG_ARRAY_REGW, // connects to csr
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.PMPADDR_ARRAY_REGW, // connects to csr
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// hptw keep i/o
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.SATP_REGW, // from csr
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.STATUS_MXR, // from csr
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.STATUS_SUM, // from csr
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.STATUS_MPRV, // from csr
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.STATUS_MPP, // from csr
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.sfencevmaM, // connects to privilege
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.LoadPageFaultM, // connects to privilege
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.StoreAmoPageFaultM, // connects to privilege
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.LoadMisalignedFaultM, // connects to privilege
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.LoadAccessFaultM, // connects to privilege
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.HPTWInstrAccessFaultM, // connects to privilege
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.StoreAmoMisalignedFaultM, // connects to privilege
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.StoreAmoAccessFaultM, // connects to privilege
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.InstrDAPageFaultF,
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.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
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.LSUStallM); // change to LSUStallM
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// *** Ross: please make EBU conditional when only supporting internal memories
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if(`BUS) begin : ebu
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ebu ebu(// IFU connections
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.clk, .reset,
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// IFU interface
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.IFUHADDR,
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.IFUHBURST,
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.IFUHTRANS,
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.IFUHREADY,
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.IFUHSIZE,
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// LSU interface
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.LSUHADDR,
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.LSUHWDATA,
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.LSUHWSTRB,
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.LSUHSIZE,
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.LSUHBURST,
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.LSUHTRANS,
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.LSUHWRITE,
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.LSUHREADY,
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// BUS interface
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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end
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hazard hzu(
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.BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
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.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
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.LSUStallM, .IFUStallF,
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.FCvtIntStallD, .FStallD,
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.DivBusyE, .FDivBusyE,
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.EcallFaultM, .BreakpointFaultM,
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.wfiM, .IntPendingM,
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// Stall & flush outputs
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushD, .FlushE, .FlushM, .FlushW
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); // global stall and flush control
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if (`ZICSR_SUPPORTED) begin:priv
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privileged priv(
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.InstrM, .CSRReadValW, .PrivilegedNextPCM,
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.RetM, .TrapM,
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.sfencevmaM,
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.InstrValidM, .CommittedM, .CommittedF,
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.FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM,
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.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
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.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT,
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.IEUAdrM,
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.SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
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.IllegalFPUInstrM,
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.PrivilegeModeW, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM
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);
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end else begin
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assign CSRReadValW = 0;
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assign PrivilegedNextPCM = 0;
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assign RetM = 0;
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assign TrapM = 0;
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assign wfiM = 0;
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assign sfencevmaM = 0;
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assign BigEndianM = 0;
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end
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if (`M_SUPPORTED) begin:mdu
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muldiv mdu(
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.clk, .reset,
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.ForwardedSrcAE, .ForwardedSrcBE,
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.Funct3E, .Funct3M, .MDUE, .W64E,
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.MDUResultW, .DivBusyE,
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.StallM, .StallW, .FlushE, .FlushM, .FlushW
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);
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end else begin // no M instructions supported
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assign MDUResultW = 0;
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assign DivBusyE = 0;
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end
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if (`F_SUPPORTED) begin:fpu
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fpu fpu(
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.clk, .reset,
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.FRM_REGW, // Rounding mode from CSR
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.InstrD, // instruction from IFU
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.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
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.ForwardedSrcAE, // Integer input being processed (from IEU)
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.StallE, .StallM, .StallW, // stall signals from HZU
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//.TrapM,
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.FlushE, .FlushM, .FlushW, // flush signals from HZU
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.RdM, .RdW, // which FP register to write to (from IEU)
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.STATUS_FS, // is floating-point enabled?
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.FRegWriteM, // FP register write enable
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.FpLoadStoreM,
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.ForwardedSrcBE, // Integer input for intdiv
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.Funct3E, .Funct3M, .MDUE, .W64E, // Integer flags and functions
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.FStallD, // Stall the decode stage
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.FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
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.FWriteDataM, // Data to be written to memory
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.FIntResM, // data to be written to integer register
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.FCvtIntResW, // fp -> int conversion result to be stored in int register
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.FCvtIntW, // fpu result selection
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.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
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.IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
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.SetFflagsM, // FPU flags (to privileged unit)
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.FPIntDivResultW
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); // floating point unit
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end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
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assign FStallD = 0;
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assign FWriteIntE = 0;
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assign FCvtIntE = 0;
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assign FIntResM = 0;
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assign FCvtIntW = 0;
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assign FDivBusyE = 0;
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assign IllegalFPUInstrM = 1;
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assign SetFflagsM = 0;
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assign FpLoadStoreM = 0;
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end
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endmodule
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