Renamed wally-pipelined to pipelined

This commit is contained in:
David Harris 2022-01-04 19:47:41 +00:00
parent 1ea267cab5
commit b36ace221e
980 changed files with 23 additions and 858 deletions

2
.gitattributes vendored
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@ -1 +1 @@
wally-pipelined/busybear_boot/* filter=lfs diff=lfs merge=lfs -text
pipelined/busybear_boot/* filter=lfs diff=lfs merge=lfs -text

6
.gitignore vendored
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@ -13,7 +13,7 @@ addins/riscv-arch-test/Makefile.include
#vsim work files to ignore
transcript
vsim.wlf
wally-pipelined/wlft*
pipelined/wlft*
wlft*
/imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr
@ -35,8 +35,8 @@ tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
wally-pipelined/regression/logs
pipelined/regression/slack-notifier/slack-webhook-url.txt
pipelined/regression/logs
fpga/generator/IP
fpga/generator/vivado.*
fpga/generator/.Xil/*

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@ -11,7 +11,7 @@ install:
echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
regression:
make -C wally-pipelined/regression
make -C pipelined/regression

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@ -16,7 +16,7 @@ a large number of debuging signals.
* Programming the flash card
You'll need to write the linux image to the flash card. Use the convert2bin.py
script in wally-pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
file from QEMU's preload to generate the binary. Then to copy
sudo dd if=ram.bin of=<path to flash card>.

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@ -14,10 +14,10 @@ read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/x
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
read_verilog -sv [glob -type f ../../wally-pipelined/src/*/*.sv ../../wally-pipelined/src/*/*/*.sv]
read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
read_verilog {../src/fpgaTop.v}
set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset]
set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc]

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@ -180,7 +180,7 @@ always @(posedge clk)
always @(negedge clk) begin
if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin
// fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
// fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w");
// if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (FMAResM != ans))) begin
$display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero ");

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@ -11,4 +11,4 @@ make XLEN=32
exe2memfile.pl work/*/*/*.elf
cd ../linux-testgen/linux-testvectors
./tvLinker.sh
cd ../../../wally-pipelined/regression
cd ../../../pipelined/regression

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