forked from Github_Repos/cvw
fixed small errors to get regression to run with bit manip supported.
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@ -34,20 +34,17 @@ module clmul #(parameter WIDTH=32) (
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output logic [WIDTH-1:0] ClmulResult); // ZBS result
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output logic [WIDTH-1:0] ClmulResult); // ZBS result
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logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products
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logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products
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// Note: only generates the bottom WIDTH bits of the carryless multiply.
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// To get the high bits or the reversed bits, the inputs can be shifted and reversed
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// as they are in zbc where this is instantiated
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genvar i,j;
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genvar i;
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for (i=1; i<WIDTH;i++) begin:outer //loop fills partial product array
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for (i=0; i<WIDTH; i++) begin
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for (j=0;j<=i;j++) begin: inner
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assign pp[i] = ((A & {(WIDTH){B[i]}}) << i); // Fill partial product array
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assign pp[i][j] = A[i]&B[j];
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// ClmulResult ^= pp[i];
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end
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end
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end
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for (i=1;i<WIDTH;i++) begin:xortree
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assign ClmulResult = pp.xor();
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assign result[i] = ^pp[i:0][i];
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end
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assign ClmulResult[0] = A[0]&B[0];
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endmodule
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endmodule
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@ -30,10 +30,14 @@ module popcnt #(parameter WIDTH = 32) (
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);
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);
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logic [$clog2(WIDTH):0] sum;
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logic [$clog2(WIDTH):0] sum;
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genvar i;
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for (i=0;i<WIDTH;i++) begin:loop
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always_comb begin
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assign sum = sum + num[i];
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sum = 0;
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for (int i=0;i<WIDTH;i++) begin:loop
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sum = sum + num[i];
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end
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end
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end
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assign PopCnt = sum;
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assign PopCnt = sum;
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@ -51,7 +51,7 @@ module zbs #(parameter WIDTH=32) (
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10'b010010?_101: ZBSResult = ExtResult;
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10'b010010?_101: ZBSResult = ExtResult;
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10'b011010?_001: ZBSResult = InvResult;
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10'b011010?_001: ZBSResult = InvResult;
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10'b001010?_001: ZBSResult = SetResult;
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10'b001010?_001: ZBSResult = SetResult;
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default: ZBSResult = 0; // *** should never be reached or selected
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default: ZBSResult = 0; // *** expand to include faults
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endcase
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endcase
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end
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end
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