From 9da1ed4ed983d3aa958d15af5c421ccb6ac0ed93 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 25 Jan 2022 19:40:07 +0000
Subject: [PATCH] simpleram simplification

---
 pipelined/src/generic/flop/simpleram.sv | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index 8e33eb8e..74fb7cd2 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -38,32 +38,23 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
   output logic [`XLEN-1:0] rd
 );
 
-  localparam MemStartAddr = BASE>>(1+`XLEN/32);
-  localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
-  
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   logic [31:0] ad;
 
-  flop #(32)   areg(clk, a, ad);
+  flop #(32)   areg(clk, a, ad); // *** redesign external interface so this delay isn't needed
   
   /* verilator lint_off WIDTH */
   if (`XLEN == 64)  begin:ramrw
     always_ff @(posedge clk) begin
+      rd <= RAM[a[31:3]];
       if (we) RAM[ad[31:3]] <= #1 wd;
     end
   end else begin 
     always_ff @(posedge clk) begin:ramrw
+      rd <= RAM[a[31:2]];
       if (we) RAM[ad[31:2]] <= #1 wd;
     end
   end
-
-  // read
-  if(`XLEN == 64) begin: ramr
-    assign rd = RAM[ad[31:3]];
-  end else begin
-    assign rd = RAM[ad[31:2]];
-  end
-
   /* verilator lint_on WIDTH */
 endmodule