From 92bb38fa8c00ec0d3599d2b8c9b68ff6efaa9733 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Thu, 15 Apr 2021 19:13:42 -0400 Subject: [PATCH] Add support for vectored interrupts --- .../config/busybear/wally-config.vh | 1 + wally-pipelined/config/rv32ic/wally-config.vh | 1 + wally-pipelined/config/rv64ic/wally-config.vh | 1 + .../config/rv64icfd/wally-config.vh | 1 + wally-pipelined/src/privileged/trap.sv | 18 ++++++++++++++---- 5 files changed, 18 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index 84a26430..298f48ac 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -56,6 +56,7 @@ `define MEM_DTIM 1 `define MEM_ICACHE 0 `define MEM_VIRTMEM 0 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. // Address space `define RESET_VECTOR 64'h0000000000001000 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index f96239e9..c3dd5387 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -54,6 +54,7 @@ `define MEM_DTIM 1 `define MEM_ICACHE 0 `define MEM_VIRTMEM 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Address space `define RESET_VECTOR 32'h80000000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 8de53dd3..c898e102 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -55,6 +55,7 @@ `define MEM_DTIM 1 `define MEM_ICACHE 0 `define MEM_VIRTMEM 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index 817c8fc1..c04b3977 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -55,6 +55,7 @@ `define MEM_DTIM 1 `define MEM_ICACHE 0 `define MEM_VIRTMEM 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 65e7260f..8452fd28 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -2,7 +2,7 @@ // trap.sv // // Written: David_Harris@hmc.edu 9 January 2021 -// Modified: +// Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts // // Purpose: Handle Traps: Exceptions and Interrupt // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 @@ -47,6 +47,7 @@ module trap ( logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM; logic InterruptM; + logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; // Determine pending enabled interrupts assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9 @@ -64,13 +65,22 @@ module trap ( assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED; assign RetM = mretM | sretM | uretM; + always_comb + if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW; + else if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; + else PrivilegedTrapVector = MTVEC_REGW; + + // Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01) + // For vectored traps, set program counter to _tvec value + 4 times the cause code + assign PrivilegedVectoredTrapVector = PrivilegedTrapVector + {CauseM[`XLEN-3:0], 2'b00}; + always_comb if (mretM) PrivilegedNextPCM = MEPC_REGW; else if (sretM) PrivilegedNextPCM = SEPC_REGW; else if (uretM) PrivilegedNextPCM = UEPC_REGW; - else if (NextPrivilegeModeM == `U_MODE) PrivilegedNextPCM = UTVEC_REGW; - else if (NextPrivilegeModeM == `S_MODE) PrivilegedNextPCM = STVEC_REGW; - else PrivilegedNextPCM = MTVEC_REGW; + else if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1) + PrivilegedNextPCM = PrivilegedVectoredTrapVector; + else PrivilegedNextPCM = PrivilegedTrapVector; // Cause priority defined in table 3.7 of 20190608 privileged spec // Exceptions are of lower priority than all interrupts (3.1.9)