diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 16960106..51e8bc90 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -233,6 +233,8 @@ module ifu (
   if (`MEM_IROM) begin : irom
 	logic [`XLEN-1:0] FinalInstrRawF_FIXME;
 
+    // *** adjust interface so write address doesn't need delaying
+    // *** modify to be a ROM rather than RAM
     simpleram #(
         .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .clk, 
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 769f50a7..93cf5e84 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -245,6 +245,7 @@ module lsu (
   logic 			   SelUncachedAdr;
 
   if (`MEM_DTIM) begin : dtim
+    // *** adjust interface so write address doesn't need delaying; switch to standard RAM?
     simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .clk, 
         .a(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),