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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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David Harris 2022-05-03 18:32:04 +00:00
commit 8a43d6099b
2 changed files with 14 additions and 21 deletions
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32
pipelined/src/cache/sram1p1rw.sv vendored
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@ -45,12 +45,9 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
logic [$clog2(DEPTH)-1:0] AdrD; logic [$clog2(DEPTH)-1:0] AdrD;
logic WriteEnableD; logic WriteEnableD;
localparam WM8 = WIDTH%8;
always_ff @(posedge clk) AdrD <= Adr; always_ff @(posedge clk) AdrD <= Adr;
integer index; genvar index;
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
for(index = 0; index < WIDTH/8; index++) begin for(index = 0; index < WIDTH/8; index++) begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
@ -61,22 +58,17 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
end end
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
always_ff @(posedge clk) begin if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
if (WriteEnable) begin always_ff @(posedge clk)
for(index = 0; index < WIDTH/8; index++) begin if (WriteEnable & ByteMask[WIDTH/8])
if(ByteMask[index]) begin StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
end
end
/* if (WM8 > 0) begin // handle msbs that aren't a multiple of 8
if (ByteMask[WIDTH/8]) begin
StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1
CacheWriteData[WIDTH-1:WIDTH-WM8];
end
end */
end
end
for(index = 0; index < WIDTH/8; index++)
always_ff @(posedge clk)
if(WriteEnable & ByteMask[index])
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
/*
// if not a multiple of 8, MSByte is not 8 bits long. // if not a multiple of 8, MSByte is not 8 bits long.
if(WIDTH%8 != 0) begin if(WIDTH%8 != 0) begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
@ -85,7 +77,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
end end
end end
end end
*/
assign ReadData = StoredData[AdrD]; assign ReadData = StoredData[AdrD];
endmodule endmodule

3
setup.sh
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@ -26,8 +26,9 @@ export PATH=$WALLY/bin:$PATH
# Verilator # Verilator
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
# ModelSim/Questa (vsim) # ModelSim/Questa (vsim)
export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim, or delete # Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks. Ues 2021.2 for now
export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH # Change this for your path to Modelsim export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH # Change this for your path to Modelsim
export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim, or delete
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler
export SNPSLMD_LICENSE_FILE=27020@134.173.38.214 export SNPSLMD_LICENSE_FILE=27020@134.173.38.214