From 20bbe43a2305f022dd9c854e09291ebf6de7e746 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 3 May 2022 08:31:54 -0700
Subject: [PATCH] clean up sram1p1rw; still doesn't work on Modelsim 2022.1

---
 pipelined/src/cache/sram1p1rw.sv | 32 ++++++++++++--------------------
 setup.sh                         |  3 ++-
 2 files changed, 14 insertions(+), 21 deletions(-)

diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv
index 7b673968..5a7da75d 100644
--- a/pipelined/src/cache/sram1p1rw.sv
+++ b/pipelined/src/cache/sram1p1rw.sv
@@ -45,12 +45,9 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   logic [$clog2(DEPTH)-1:0]       AdrD;
   logic                           WriteEnableD;
 
-  localparam WM8 = WIDTH%8;
-   
-
   always_ff @(posedge clk)       AdrD <= Adr;
 
-  integer                          index;
+  genvar                          index;
 /* -----\/----- EXCLUDED -----\/-----
   for(index = 0; index < WIDTH/8; index++) begin
     always_ff @(posedge clk) begin
@@ -61,22 +58,17 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   end
  -----/\----- EXCLUDED -----/\----- */
 
-  always_ff @(posedge clk) begin
-    if (WriteEnable) begin
-      for(index = 0; index < WIDTH/8; index++) begin
-        if(ByteMask[index]) begin
-           StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
-        end
-      end
-/*      if (WM8 > 0) begin  // handle msbs that aren't a multiple of 8
-	if (ByteMask[WIDTH/8]) begin
-	  StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1 
-	    CacheWriteData[WIDTH-1:WIDTH-WM8];
-	end
-      end */
-    end
-  end
+  if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
+    always_ff @(posedge clk) 
+      if (WriteEnable & ByteMask[WIDTH/8])
+        StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 
+	  CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
   
+  for(index = 0; index < WIDTH/8; index++) 
+    always_ff @(posedge clk)
+      if(WriteEnable & ByteMask[index])
+	StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
+/*  
   // if not a multiple of 8, MSByte is not 8 bits long.
   if(WIDTH%8 != 0) begin
     always_ff @(posedge clk) begin
@@ -85,7 +77,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
       end
     end
   end 
-
+*/
   assign ReadData = StoredData[AdrD];
 endmodule
 
diff --git a/setup.sh b/setup.sh
index b3452626..b3f9fb11 100755
--- a/setup.sh
+++ b/setup.sh
@@ -26,8 +26,9 @@ export PATH=$WALLY/bin:$PATH
 # Verilator
 export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
 # ModelSim/Questa (vsim)
-export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH    # Change this for your path to Modelsim, or delete
+# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks.  Ues 2021.2 for now
 export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH    # Change this for your path to Modelsim 
+export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH    # Change this for your path to Modelsim, or delete
 export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
 export PATH=/cad/synopsys/SYN/bin:$PATH  # Change this for your path to Design Compiler
 export SNPSLMD_LICENSE_FILE=27020@134.173.38.214