diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md
index a25b3a18..37390a63 100644
--- a/docs/testplans/testplan.md
+++ b/docs/testplans/testplan.md
@@ -1,6 +1,29 @@
-# CORE-V Wally Test Plan
+# CORE-V Wally Design Verification Test Plan
+
+CORE-V Wally is functionally tested in the following ways.  Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
+
+| Functions      | Coverage Method | Status |
+| ----------- | ----------- |----|
+|  Instructions | riscv-arch-test | Pass   |
+| Privileged Unit   | wally-riscv-arch-test        | Pass   |
+| Virtual Memory | wally-riscv-arch-test | Pass |
+| PMP | wally-riscv-arch-test | Pass
+| Peripherals | wally-riscv-arch-test | Pass |
+| Floating-Point | TestFloat | Pass |
+| General | Code Coverage | 91% |
+| General | Boot Linux in Sim | Pass | 
+| General | Boot Linux on FPGA | Pass |
+
+
+The following performance validation is also run:
+| Function | Method | Status |
+| --- | --- | --- |
+| Overall Performance | embench | Pass|
+| Overall Performance | coremark | Pass |
+| Branch Predictor | *** | Pass |
+| Cache Miss Rate | *** | Pass |
+
 
-CORE-V Wally is tested in the following ways:
 
 * Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
 * Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.