forked from Github_Repos/cvw
Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way.
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96781e0b2a
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@ -53,6 +53,42 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe6]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list c0_init_calib_complete ]]
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connect_debug_port u_ila_0/probe6 [get_nets [list c0_init_calib_complete ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe7]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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connect_debug_port u_ila_0/probe7 [get_nets [list bus_struct_reset ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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connect_debug_port u_ila_0/probe8 [get_nets [list peripheral_reset ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe9]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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connect_debug_port u_ila_0/probe9 [get_nets [list interconnect_aresetn ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe10]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
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connect_debug_port u_ila_0/probe10 [get_nets [list peripheral_aresetn ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe11]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
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connect_debug_port u_ila_0/probe11 [get_nets [list mb_reset ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe12]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
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connect_debug_port u_ila_0/probe12 [get_nets [list resetn ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe13]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
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connect_debug_port u_ila_0/probe13 [get_nets [list c0_ddr4_ui_clk_sync_rst ]]
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# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
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# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
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#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
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#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
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@ -28,7 +28,7 @@
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module fpgaTop
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module fpgaTop
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(input default_100mhz_clk,
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(input default_100mhz_clk,
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input reset,
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(* mark_debug = "true" *) input resetn,
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input [3:0] GPI,
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input [3:0] GPI,
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output [4:0] GPO,
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output [4:0] GPO,
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@ -58,12 +58,12 @@ module fpgaTop
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);
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);
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wire CPUCLK;
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wire CPUCLK;
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wire c0_ddr4_ui_clk_sync_rst;
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(* mark_debug = "true" *) wire c0_ddr4_ui_clk_sync_rst;
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wire bus_struct_reset;
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(* mark_debug = "true" *) wire bus_struct_reset;
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wire peripheral_reset;
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(* mark_debug = "true" *) wire peripheral_reset;
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wire interconnect_aresetn;
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(* mark_debug = "true" *) wire interconnect_aresetn;
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wire peripheral_aresetn;
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(* mark_debug = "true" *) wire peripheral_aresetn;
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wire mb_reset;
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(* mark_debug = "true" *) wire mb_reset;
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wire HCLKOpen;
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wire HCLKOpen;
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wire HRESETnOpen;
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wire HRESETnOpen;
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@ -214,7 +214,7 @@ module fpgaTop
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xlnx_proc_sys_reset xlnx_proc_sys_reset_0
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xlnx_proc_sys_reset xlnx_proc_sys_reset_0
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(.slowest_sync_clk(CPUCLK),
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(.slowest_sync_clk(CPUCLK),
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.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
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.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
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.aux_reset_in(south_rst),
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.aux_reset_in(1'b0),
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.mb_debug_sys_rst(1'b0),
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.mb_debug_sys_rst(1'b0),
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.dcm_locked(c0_init_calib_complete),
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.dcm_locked(c0_init_calib_complete),
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.mb_reset(mb_reset), //open
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.mb_reset(mb_reset), //open
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@ -353,7 +353,7 @@ module fpgaTop
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.s_axi_rready(m_axi_rready),
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.s_axi_rready(m_axi_rready),
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.m_axi_aclk(BUSCLK),
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.m_axi_aclk(BUSCLK),
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.m_axi_aresetn(~reset),
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.m_axi_aresetn(resetn),
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.m_axi_awid(BUS_axi_awid),
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.m_axi_awid(BUS_axi_awid),
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.m_axi_awlen(BUS_axi_awlen),
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.m_axi_awlen(BUS_axi_awlen),
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.m_axi_awsize(BUS_axi_awsize),
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.m_axi_awsize(BUS_axi_awsize),
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@ -421,8 +421,8 @@ module fpgaTop
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.ui_clk(BUSCLK),
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.ui_clk(BUSCLK),
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.ui_clk_sync_rst(ui_clk_sync_rst),
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.ui_clk_sync_rst(ui_clk_sync_rst),
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.aresetn(~reset),
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.aresetn(resetn),
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.sys_rst(reset),
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.sys_rst(~resetn),
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.mmcm_locked(mmcm_locked),
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.mmcm_locked(mmcm_locked),
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// *** What are these?
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// *** What are these?
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