diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc
index 30d2db51..4d943b5f 100644
--- a/fpga/constraints/small-debug.xdc
+++ b/fpga/constraints/small-debug.xdc
@@ -53,6 +53,42 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe6]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
 connect_debug_port u_ila_0/probe6 [get_nets [list c0_init_calib_complete ]]
 
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list bus_struct_reset ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list peripheral_reset ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list interconnect_aresetn ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list peripheral_aresetn ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list mb_reset ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list resetn ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list c0_ddr4_ui_clk_sync_rst ]]
+
 
 # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
 #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v
index 6c3dcc7a..915d5827 100644
--- a/fpga/src/fpgaTopArtyA7.v
+++ b/fpga/src/fpgaTopArtyA7.v
@@ -28,7 +28,7 @@
 
 module fpgaTop 
   (input           default_100mhz_clk,
-   input           reset,
+(* mark_debug = "true" *)   input           resetn,
 
    input [3:0]     GPI,
    output [4:0]    GPO,
@@ -58,12 +58,12 @@ module fpgaTop
    );
 
   wire 			   CPUCLK;
-  wire 			   c0_ddr4_ui_clk_sync_rst;
-  wire 			   bus_struct_reset;
-  wire 			   peripheral_reset;
-  wire 			   interconnect_aresetn;
-  wire 			   peripheral_aresetn;
-  wire 			   mb_reset;
+(* mark_debug = "true" *)  wire 			   c0_ddr4_ui_clk_sync_rst;
+(* mark_debug = "true" *)  wire 			   bus_struct_reset;
+(* mark_debug = "true" *)  wire 			   peripheral_reset;
+(* mark_debug = "true" *)  wire 			   interconnect_aresetn;
+(* mark_debug = "true" *)  wire 			   peripheral_aresetn;
+(* mark_debug = "true" *)  wire 			   mb_reset;
   
   wire 			   HCLKOpen;
   wire 			   HRESETnOpen;
@@ -214,7 +214,7 @@ module fpgaTop
   xlnx_proc_sys_reset xlnx_proc_sys_reset_0
     (.slowest_sync_clk(CPUCLK),
      .ext_reset_in(c0_ddr4_ui_clk_sync_rst),
-     .aux_reset_in(south_rst),
+     .aux_reset_in(1'b0),
      .mb_debug_sys_rst(1'b0),
      .dcm_locked(c0_init_calib_complete),
      .mb_reset(mb_reset),  //open
@@ -353,7 +353,7 @@ module fpgaTop
      .s_axi_rready(m_axi_rready),
 
      .m_axi_aclk(BUSCLK),
-     .m_axi_aresetn(~reset),
+     .m_axi_aresetn(resetn),
      .m_axi_awid(BUS_axi_awid),
      .m_axi_awlen(BUS_axi_awlen),
      .m_axi_awsize(BUS_axi_awsize),
@@ -421,8 +421,8 @@ module fpgaTop
 
      .ui_clk(BUSCLK),
      .ui_clk_sync_rst(ui_clk_sync_rst),
-     .aresetn(~reset),
-     .sys_rst(reset),
+     .aresetn(resetn),
+     .sys_rst(~resetn),
      .mmcm_locked(mmcm_locked),
 
      // *** What are these?