From 802238643aeb2fe46168f31f7702cde95022456a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 10 Jun 2021 10:30:24 -0400
Subject: [PATCH] Removed two cycles of latency from the DTIM

---
 wally-pipelined/src/uncore/dtim.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
index bcb1eb9d..6b474dae 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -69,7 +69,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
         busycount <= 0;
         HREADYTim <= #1 0;
       end else if (~HREADYTim) begin
-        if (busycount == 2) begin // TIM latency, for testing purposes.  *** test with different values
+        if (busycount == 0) begin // TIM latency, for testing purposes.  *** test with different values such as 2
           HREADYTim <= #1 1;
         end else begin
           busycount <= busycount + 1;