forked from Github_Repos/cvw
More branch predictor cleanup.
This commit is contained in:
parent
65dd86b726
commit
78e441fb38
@ -140,7 +140,7 @@
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`define PLIC_UART_ID 10
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`define PLIC_UART_ID 10
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`define BPRED_ENABLED 1
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`define BPRED_ENABLED 1
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`define BPTYPE "BPOLDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE
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`define BPTYPE "BPOLDGSHARE2" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE
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`define TESTSBP 0
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`define TESTSBP 0
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`define BPRED_SIZE 10
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`define BPRED_SIZE 10
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@ -594,8 +594,10 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Ta
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewGHRF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewGHRF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPInstrClassE
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {2156 ns} 0}
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WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {2086 ns} 0}
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quietly wave cursor active 5
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quietly wave cursor active 5
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configure wave -namecolwidth 250
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 194
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configure wave -valuecolwidth 194
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@ -611,4 +613,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timeline 0
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configure wave -timelineunits ns
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configure wave -timelineunits ns
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update
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update
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WaveRestoreZoom {1955 ns} {2357 ns}
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WaveRestoreZoom {1919 ns} {2207 ns}
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@ -63,7 +63,7 @@ module bpred (
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output logic DirPredictionWrongM, // Prediction direction is wrong.
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output logic DirPredictionWrongM, // Prediction direction is wrong.
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output logic BTBPredPCWrongM, // Prediction target wrong.
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output logic BTBPredPCWrongM, // Prediction target wrong.
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output logic RASPredPCWrongM, // RAS prediction is wrong.
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output logic RASPredPCWrongM, // RAS prediction is wrong.
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output logic BPPredClassNonCFIWrongM // Class prediction is wrong.
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output logic PredictionInstrClassWrongM // Class prediction is wrong.
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);
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);
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logic BTBValidF;
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logic BTBValidF;
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@ -114,7 +114,13 @@ module bpred (
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.BranchInstrW(InstrClassW[0]), .PCSrcE);
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.BranchInstrW(InstrClassW[0]), .PCSrcE);
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end else if (`BPTYPE == "BPOLDGSHARE") begin:Predictor
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end else if (`BPTYPE == "BPOLDGSHARE") begin:Predictor
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oldgsharePredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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oldgsharepredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BPInstrClassF, .BPInstrClassD, .BPInstrClassE,
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.InstrClassE, .PCSrcE);
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end else if (`BPTYPE == "BPOLDGSHARE2") begin:Predictor
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oldgsharepredictor2 DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BPInstrClassF, .BPInstrClassD, .BPInstrClassE,
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.BPInstrClassF, .BPInstrClassD, .BPInstrClassE,
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.InstrClassE, .PCSrcE);
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.InstrClassE, .PCSrcE);
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@ -187,8 +193,8 @@ module bpred (
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// branch predictor
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// branch predictor
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flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
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flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
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{DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE},
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{DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
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{DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM});
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{DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
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// pipeline the class
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// pipeline the class
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flopenrc #(5) BPInstrClassRegD(clk, reset, FlushD, ~StallD, BPInstrClassF, BPInstrClassD);
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flopenrc #(5) BPInstrClassRegD(clk, reset, FlushD, ~StallD, BPInstrClassF, BPInstrClassD);
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@ -224,6 +230,7 @@ module bpred (
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// Finally if the real instruction class is non CFI but the predictor said it was we need to count.
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// Finally if the real instruction class is non CFI but the predictor said it was we need to count.
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assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
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assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
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// Selects the BP or PC+2/4.
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// Selects the BP or PC+2/4.
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mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
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mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
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// If the prediction is wrong select the correct address.
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// If the prediction is wrong select the correct address.
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@ -1,134 +0,0 @@
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///////////////////////////////////////////
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// globalHistoryPredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Gshare predictor with parameterized global history register
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module oldgsharePredictor
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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output logic [1:0] DirPredictionF,
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// update
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input logic [4:0] InstrClassE,
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input logic [4:0] BPInstrClassE,
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input logic [4:0] BPInstrClassD,
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input logic [4:0] BPInstrClassF,
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output logic DirPredictionWrongE,
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input logic PCSrcE
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);
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logic [`BPRED_SIZE+1:0] GHR, GHRNext;
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logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
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logic PHTUpdateEN;
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logic BPClassWrongNonCFI;
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logic BPClassWrongCFI;
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logic BPClassRightNonCFI;
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logic BPClassRightBPWrong;
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logic BPClassRightBPRight;
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logic [1:0] DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionE;
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logic [6:0] GHRMuxSel;
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logic GHRUpdateEN;
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logic [`BPRED_SIZE-1:0] GHRLookup;
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assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
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assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
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assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
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assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
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assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
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// GHR update selection, 1 hot encoded.
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assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
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assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
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assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
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assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
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assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
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assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
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assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
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assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
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// hoping this created a AND-OR mux.
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always_comb begin
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case (GHRMuxSel)
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7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change
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7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
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7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
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7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
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7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
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7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
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7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
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default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
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endcase
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end
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flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
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.reset(reset),
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.en((GHRUpdateEN)),
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.d(GHRNext),
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.q(GHR));
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// if actively updating the GHR at the time of prediction we want to us
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// GHRNext as the lookup rather than GHR.
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assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
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assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];
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assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
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assign PHTUpdateEN = InstrClassE[0] & ~StallE;
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assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
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// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
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ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
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.reset(reset),
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//.RA1(GHR[`BPRED_SIZE-1:0]),
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.ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
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.rd1(DirPredictionF),
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.ren1(~StallF),
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.wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
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.wd2(NewDirPredictionE),
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.wen2(PHTUpdateEN),
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.bwe2(2'b11));
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// DirPrediction pipeline
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flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
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// New prediction pipeline
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
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endmodule // gsharePredictor
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@ -65,7 +65,7 @@ module ifu (
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output logic DirPredictionWrongM,
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output logic DirPredictionWrongM,
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output logic BTBPredPCWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic BPPredClassNonCFIWrongM,
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output logic PredictionInstrClassWrongM,
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// Faults
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// Faults
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input logic IllegalBaseInstrFaultD,
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input logic IllegalBaseInstrFaultD,
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output logic InstrPageFaultF,
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output logic InstrPageFaultF,
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@ -325,12 +325,12 @@ module ifu (
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.FlushD, .FlushE, .FlushM, .FlushW,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
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.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
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end else begin : bpred
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end else begin : bpred
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mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F));
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mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F));
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assign BPPredWrongE = PCSrcE;
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assign BPPredWrongE = PCSrcE;
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assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0;
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assign PCNext0F = PCPlus2or4F;
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assign PCNext0F = PCPlus2or4F;
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assign NextValidPCE = PCE;
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assign NextValidPCE = PCE;
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end
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end
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@ -48,7 +48,7 @@ module csr #(parameter
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input logic DirPredictionWrongM,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic BPPredClassNonCFIWrongM,
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input logic PredictionInstrClassWrongM,
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input logic [4:0] InstrClassM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic DCacheAccess,
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@ -214,7 +214,7 @@ module csr #(parameter
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csrc counters(.clk, .reset,
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csrc counters(.clk, .reset,
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.StallE, .StallM, .StallW, .FlushM,
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.StallE, .StallM, .StallW, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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@ -48,7 +48,7 @@ module csrc #(parameter
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input logic DirPredictionWrongM,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
|
input logic BTBPredPCWrongM,
|
||||||
input logic RASPredPCWrongM,
|
input logic RASPredPCWrongM,
|
||||||
input logic BPPredClassNonCFIWrongM,
|
input logic PredictionInstrClassWrongM,
|
||||||
input logic [4:0] InstrClassM,
|
input logic [4:0] InstrClassM,
|
||||||
input logic DCacheMiss,
|
input logic DCacheMiss,
|
||||||
input logic DCacheAccess,
|
input logic DCacheAccess,
|
||||||
@ -92,7 +92,7 @@ module csrc #(parameter
|
|||||||
assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & InstrValidNotFlushedM;
|
assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & InstrValidNotFlushedM;
|
||||||
assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
|
assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
|
||||||
assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM;
|
assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM;
|
||||||
assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
|
assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;
|
||||||
assign CounterEvent[11] = DCacheAccess;
|
assign CounterEvent[11] = DCacheAccess;
|
||||||
assign CounterEvent[12] = DCacheMiss;
|
assign CounterEvent[12] = DCacheMiss;
|
||||||
assign CounterEvent[13] = ICacheAccess;
|
assign CounterEvent[13] = ICacheAccess;
|
||||||
|
@ -44,7 +44,7 @@ module privileged (
|
|||||||
input logic DirPredictionWrongM,
|
input logic DirPredictionWrongM,
|
||||||
input logic BTBPredPCWrongM,
|
input logic BTBPredPCWrongM,
|
||||||
input logic RASPredPCWrongM,
|
input logic RASPredPCWrongM,
|
||||||
input logic BPPredClassNonCFIWrongM,
|
input logic PredictionInstrClassWrongM,
|
||||||
input logic [4:0] InstrClassM,
|
input logic [4:0] InstrClassM,
|
||||||
input logic DCacheMiss,
|
input logic DCacheMiss,
|
||||||
input logic DCacheAccess,
|
input logic DCacheAccess,
|
||||||
@ -129,7 +129,7 @@ module privileged (
|
|||||||
.MTIME_CLINT,
|
.MTIME_CLINT,
|
||||||
.InstrValidM, .FRegWriteM, .LoadStallD,
|
.InstrValidM, .FRegWriteM, .LoadStallD,
|
||||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
|
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
|
||||||
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
|
.PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
|
||||||
.NextPrivilegeModeM, .PrivilegeModeW,
|
.NextPrivilegeModeM, .PrivilegeModeW,
|
||||||
.CauseM, .SelHPTW,
|
.CauseM, .SelHPTW,
|
||||||
.STATUS_MPP,
|
.STATUS_MPP,
|
||||||
|
@ -151,7 +151,7 @@ module wallypipelinedcore (
|
|||||||
logic DirPredictionWrongM;
|
logic DirPredictionWrongM;
|
||||||
logic BTBPredPCWrongM;
|
logic BTBPredPCWrongM;
|
||||||
logic RASPredPCWrongM;
|
logic RASPredPCWrongM;
|
||||||
logic BPPredClassNonCFIWrongM;
|
logic PredictionInstrClassWrongM;
|
||||||
logic [4:0] InstrClassM;
|
logic [4:0] InstrClassM;
|
||||||
logic InstrAccessFaultF, HPTWInstrAccessFaultM;
|
logic InstrAccessFaultF, HPTWInstrAccessFaultM;
|
||||||
logic [2:0] LSUHSIZE;
|
logic [2:0] LSUHSIZE;
|
||||||
@ -185,7 +185,7 @@ module wallypipelinedcore (
|
|||||||
// Mem
|
// Mem
|
||||||
.RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
|
.RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
|
||||||
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
|
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
|
||||||
.BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
.BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||||
|
|
||||||
// Writeback
|
// Writeback
|
||||||
|
|
||||||
@ -341,7 +341,7 @@ module wallypipelinedcore (
|
|||||||
.InstrValidM, .CommittedM, .CommittedF,
|
.InstrValidM, .CommittedM, .CommittedF,
|
||||||
.FRegWriteM, .LoadStallD,
|
.FRegWriteM, .LoadStallD,
|
||||||
.DirPredictionWrongM, .BTBPredPCWrongM,
|
.DirPredictionWrongM, .BTBPredPCWrongM,
|
||||||
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
.RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
|
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
|
||||||
|
Loading…
Reference in New Issue
Block a user