From 78e441fb38ebcb933e14e6502296b693da64afc9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 5 Jan 2023 17:19:27 -0600 Subject: [PATCH] More branch predictor cleanup. --- pipelined/config/rv64gc/wally-config.vh | 2 +- pipelined/regression/wave.do | 6 +- pipelined/src/ifu/bpred.sv | 17 ++- pipelined/src/ifu/gsharePredictor.sv | 134 ---------------------- pipelined/src/ifu/ifu.sv | 6 +- pipelined/src/privileged/csr.sv | 4 +- pipelined/src/privileged/csrc.sv | 4 +- pipelined/src/privileged/privileged.sv | 4 +- pipelined/src/wally/wallypipelinedcore.sv | 6 +- 9 files changed, 29 insertions(+), 154 deletions(-) delete mode 100644 pipelined/src/ifu/gsharePredictor.sv diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 9f135d8e..f1f45010 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -140,7 +140,7 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPOLDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE +`define BPTYPE "BPOLDGSHARE2" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 78260996..d9a75158 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -594,8 +594,10 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Ta add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewGHRF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPInstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {2156 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {2086 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -611,4 +613,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1955 ns} {2357 ns} +WaveRestoreZoom {1919 ns} {2207 ns} diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index a0d77831..e83ae761 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -63,7 +63,7 @@ module bpred ( output logic DirPredictionWrongM, // Prediction direction is wrong. output logic BTBPredPCWrongM, // Prediction target wrong. output logic RASPredPCWrongM, // RAS prediction is wrong. - output logic BPPredClassNonCFIWrongM // Class prediction is wrong. + output logic PredictionInstrClassWrongM // Class prediction is wrong. ); logic BTBValidF; @@ -114,9 +114,15 @@ module bpred ( .BranchInstrW(InstrClassW[0]), .PCSrcE); end else if (`BPTYPE == "BPOLDGSHARE") begin:Predictor - oldgsharePredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + oldgsharepredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, - .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, + .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, + .InstrClassE, .PCSrcE); + + end else if (`BPTYPE == "BPOLDGSHARE2") begin:Predictor + oldgsharepredictor2 DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, .InstrClassE, .PCSrcE); end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor // *** Fix me @@ -187,8 +193,8 @@ module bpred ( // branch predictor flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}, - {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}); + {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE}, + {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); // pipeline the class flopenrc #(5) BPInstrClassRegD(clk, reset, FlushD, ~StallD, BPInstrClassF, BPInstrClassD); @@ -224,6 +230,7 @@ module bpred ( // Finally if the real instruction class is non CFI but the predictor said it was we need to count. assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; + // Selects the BP or PC+2/4. mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); // If the prediction is wrong select the correct address. diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv deleted file mode 100644 index 05a95264..00000000 --- a/pipelined/src/ifu/gsharePredictor.sv +++ /dev/null @@ -1,134 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Gshare predictor with parameterized global history register -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -module oldgsharePredictor - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - output logic [1:0] DirPredictionF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - output logic DirPredictionWrongE, - - input logic PCSrcE - - ); - logic [`BPRED_SIZE+1:0] GHR, GHRNext; - logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [`BPRED_SIZE-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update - default: GHRNext = GHR[`BPRED_SIZE-1+2:0]; - endcase - end - - flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[`BPRED_SIZE-1:0]), - .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), - .rd1(DirPredictionF), - .ren1(~StallF), - .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]), - .wd2(NewDirPredictionE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule // gsharePredictor diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index a2d7a98a..b7fa6f55 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -65,7 +65,7 @@ module ifu ( output logic DirPredictionWrongM, output logic BTBPredPCWrongM, output logic RASPredPCWrongM, - output logic BPPredClassNonCFIWrongM, + output logic PredictionInstrClassWrongM, // Faults input logic IllegalBaseInstrFaultD, output logic InstrPageFaultF, @@ -325,12 +325,12 @@ module ifu ( .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F)); assign BPPredWrongE = PCSrcE; - assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; + assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0; assign PCNext0F = PCPlus2or4F; assign NextValidPCE = PCE; end diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 608fe274..34c726ea 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -48,7 +48,7 @@ module csr #(parameter input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, + input logic PredictionInstrClassWrongM, input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, @@ -214,7 +214,7 @@ module csr #(parameter csrc counters(.clk, .reset, .StallE, .StallM, .StallW, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index d55b6cad..04f5c209 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -48,7 +48,7 @@ module csrc #(parameter input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, + input logic PredictionInstrClassWrongM, input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, @@ -92,7 +92,7 @@ module csrc #(parameter assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & InstrValidNotFlushedM; assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM; assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM; - assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM; + assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; assign CounterEvent[11] = DCacheAccess; assign CounterEvent[12] = DCacheMiss; assign CounterEvent[13] = ICacheAccess; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 18c0a82e..a1443dff 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -44,7 +44,7 @@ module privileged ( input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, + input logic PredictionInstrClassWrongM, input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, @@ -129,7 +129,7 @@ module privileged ( .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, - .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, + .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, .STATUS_MPP, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 12e6d562..794a2742 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -151,7 +151,7 @@ module wallypipelinedcore ( logic DirPredictionWrongM; logic BTBPredPCWrongM; logic RASPredPCWrongM; - logic BPPredClassNonCFIWrongM; + logic PredictionInstrClassWrongM; logic [4:0] InstrClassM; logic InstrAccessFaultF, HPTWInstrAccessFaultM; logic [2:0] LSUHSIZE; @@ -185,7 +185,7 @@ module wallypipelinedcore ( // Mem .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, - .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, + .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, // Writeback @@ -341,7 +341,7 @@ module wallypipelinedcore ( .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, .DirPredictionWrongM, .BTBPredPCWrongM, - .RASPredPCWrongM, .BPPredClassNonCFIWrongM, + .RASPredPCWrongM, .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD,