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Ross Thompson 2022-09-20 09:49:53 -05:00
parent ea6b687f7c
commit 7470bf7c7c
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pipelined/src/lsu/lsu.sv
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@ -215,6 +215,7 @@ module lsu (
assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
/* verilator lint_on WIDTH */
// *** add ce to bram1... to remove this extra mux control.
dtim dtim(.clk, .reset, .MemRWM,
.Adr(DTIMAdr),