From 7470bf7c7c61b9cd3b691d94256d28b9c23a0222 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 20 Sep 2022 09:49:53 -0500
Subject: [PATCH] Added comment.

---
 pipelined/src/lsu/lsu.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index a269d1a8..1237b7ea 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -215,6 +215,7 @@ module lsu (
     assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
     assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
+    // *** add ce to bram1... to remove this extra mux control.
 
     dtim dtim(.clk, .reset, .MemRWM,
               .Adr(DTIMAdr),