diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index a269d1a8..1237b7ea 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -215,6 +215,7 @@ module lsu (
     assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
     assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
+    // *** add ce to bram1... to remove this extra mux control.
 
     dtim dtim(.clk, .reset, .MemRWM,
               .Adr(DTIMAdr),