From 4eaf95de6081a6a43c845e796818903502bebcb2 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 21 Jul 2021 14:44:43 -0400 Subject: [PATCH 1/2] Fixed TLB parameterization and valid bit flop to correctly do instr page faults --- wally-pipelined/src/mmu/tlb.sv | 3 +-- wally-pipelined/src/mmu/tlbcamline.sv | 2 +- wally-pipelined/src/mmu/tlbcontrol.sv | 4 +--- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 2de817a5..d5c46ab0 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -101,14 +101,13 @@ module tlb #(parameter TLB_ENTRIES = 8, logic [7:0] PTEAccessBits; logic [11:0] PageOffset; - logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits logic [1:0] HitPageType; logic CAMHit; logic SV39Mode; assign VPN = Address[`VPN_BITS+11:12]; - tlbcontrol tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, .SV39Mode, .Translate); diff --git a/wally-pipelined/src/mmu/tlbcamline.sv b/wally-pipelined/src/mmu/tlbcamline.sv index 0044d760..445c717f 100644 --- a/wally-pipelined/src/mmu/tlbcamline.sv +++ b/wally-pipelined/src/mmu/tlbcamline.sv @@ -101,6 +101,6 @@ module tlbcamline #(parameter KEY_BITS = 20, // On a flush, zero the valid bit and leave the key unchanged. // *** Might we want to update stored key right away to output match on the // write cycle? (using a mux) - flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid); + flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid); flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key); endmodule diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv index cd938625..c0b41d94 100644 --- a/wally-pipelined/src/mmu/tlbcontrol.sv +++ b/wally-pipelined/src/mmu/tlbcontrol.sv @@ -25,9 +25,7 @@ `include "wally-config.vh" -// The TLB will have 2**ENTRY_BITS total entries -module tlbcontrol #(parameter TLB_ENTRIES = 8, - parameter ITLB = 0) ( +module tlbcontrol #(parameter ITLB = 0) ( // Current value of satp CSR (from privileged unit) input logic [`SVMODE_BITS-1:0] SATP_MODE,