Added Physical Address and Size to PMA Checker/MMU

This commit is contained in:
David Harris 2021-06-21 01:27:02 -04:00
parent 1ec90a5e1f
commit 5d6dc82db2
4 changed files with 5 additions and 2 deletions

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@ -95,7 +95,7 @@ module dmem (
logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .Size(Funct3M[1:0]),
.PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
.TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),

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@ -114,7 +114,7 @@ module ifu (
assign PCPF = {8'b0, PCPFmmu};
endgenerate
mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .Size(2'b10),
.PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF),
.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF),

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@ -47,6 +47,7 @@ module mmu #(parameter ENTRY_BITS = 3,
// Virtual address input
input logic [`XLEN-1:0] VirtualAddress,
input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
// Controls for writing a new entry to the TLB
input logic [`XLEN-1:0] PTEWriteVal,

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@ -30,6 +30,8 @@
module pmachecker (
// input logic clk, reset, // *** unused in this module and all sub modules.
input logic [`PA_BITS-1:0] PhysicalAddress,
input logic [1:0] Size,
input logic [31:0] HADDR,
input logic [2:0] HSIZE,
// input logic [2:0] HBURST, // *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.