diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv
index e8739cb2..7f19bc78 100644
--- a/wally-pipelined/src/dmem/dmem.sv
+++ b/wally-pipelined/src/dmem/dmem.sv
@@ -95,7 +95,7 @@ module dmem (
   logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
   // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
   
-  mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
+  mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .Size(Funct3M[1:0]),
                 .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
                 .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
                 .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 8538d7fb..b4b1b392 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -114,7 +114,7 @@ module ifu (
       assign PCPF = {8'b0, PCPFmmu};
   endgenerate
 
-  mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
+  mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .Size(2'b10),
                 .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF),
                 .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
                 .PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF),
diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv
index ce1d8b0b..ff315f12 100644
--- a/wally-pipelined/src/mmu/mmu.sv
+++ b/wally-pipelined/src/mmu/mmu.sv
@@ -47,6 +47,7 @@ module mmu #(parameter ENTRY_BITS = 3,
 
   // Virtual address input
   input logic  [`XLEN-1:0] VirtualAddress,
+  input logic  [1:0]       Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
 
   // Controls for writing a new entry to the TLB
   input logic  [`XLEN-1:0] PTEWriteVal,
diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv
index 703bb81b..d771839e 100644
--- a/wally-pipelined/src/mmu/pmachecker.sv
+++ b/wally-pipelined/src/mmu/pmachecker.sv
@@ -30,6 +30,8 @@
 module pmachecker (
 //  input  logic        clk, reset, // *** unused in this module and all sub modules.
 
+  input  logic [`PA_BITS-1:0] PhysicalAddress,
+  input  logic [1:0]          Size,
   input  logic [31:0] HADDR,
   input  logic [2:0]  HSIZE,
 //  input  logic [2:0]  HBURST, //  *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.