forked from Github_Repos/cvw
Moved more muxes inside bp.
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@ -43,8 +43,13 @@ module bpred
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input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
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input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
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input logic [`XLEN-1:0] PCPlus2or4F,
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input logic [`XLEN-1:0] PCPlus2or4F,
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output logic [`XLEN-1:0] PCNext0F,
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output logic [`XLEN-1:0] PCNext0F,
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output logic [`XLEN-1:0] PCCorrectE,
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output logic [`XLEN-1:0] PCBPWrongInvalidate, // The address of the currently executing instruction
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// Update Predictor
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// Update Predictor
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input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
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input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
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input logic [`XLEN-1:0] PCF, // The address of the currently executing instruction
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// 1 hot encoding
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// 1 hot encoding
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// return, jump register, jump, branch
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// return, jump register, jump, branch
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// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
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// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
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@ -57,7 +62,6 @@ module bpred
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output logic [4:0] InstrClassM,
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output logic [4:0] InstrClassM,
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// Report branch prediction status
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// Report branch prediction status
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output logic BPPredWrongE,
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output logic BPPredWrongE,
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output logic BPPredWrongM,
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output logic BPPredDirWrongM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic RASPredPCWrongM,
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@ -78,6 +82,8 @@ module bpred
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logic SelBPPredF;
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF;
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logic [`XLEN-1:0] BPPredPCF;
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logic BPPredWrongM;
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@ -256,6 +262,11 @@ module bpred
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
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.s(BPPredWrongM), .y(PCBPWrongInvalidate));
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endmodule
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endmodule
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@ -305,19 +305,13 @@ module ifu (
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// Branch and Jump Predictor
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// Branch and Jump Predictor
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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if (`BPRED_ENABLED) begin : bpred
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if (`BPRED_ENABLED) begin : bpred
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logic BPPredWrongM;
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bpred bpred(.clk, .reset,
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bpred bpred(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM,
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.StallF, .StallD, .StallE, .StallM,
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.FlushD, .FlushE, .FlushM,
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.FlushD, .FlushE, .FlushM,
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.InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE,
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.InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .PCBPWrongInvalidate,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
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.s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
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end else begin : bpred
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end else begin : bpred
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assign BPPredWrongE = PCSrcE;
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assign BPPredWrongE = PCSrcE;
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assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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