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Moved more muxes inside bp.

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This commit is contained in:
Ross Thompson 2022-12-19 22:51:55 -06:00
parent d8ee0ea59d
commit 565585b35a
2 changed files with 14 additions and 9 deletions
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13
pipelined/src/ifu/bpred.sv
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@ -43,8 +43,13 @@ module bpred
input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
input logic [`XLEN-1:0] PCPlus2or4F, input logic [`XLEN-1:0] PCPlus2or4F,
output logic [`XLEN-1:0] PCNext0F, output logic [`XLEN-1:0] PCNext0F,
output logic [`XLEN-1:0] PCCorrectE,
output logic [`XLEN-1:0] PCBPWrongInvalidate, // The address of the currently executing instruction
// Update Predictor // Update Predictor
input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
input logic [`XLEN-1:0] PCF, // The address of the currently executing instruction
// 1 hot encoding // 1 hot encoding
// return, jump register, jump, branch // return, jump register, jump, branch
// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class. // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
@ -57,7 +62,6 @@ module bpred
output logic [4:0] InstrClassM, output logic [4:0] InstrClassM,
// Report branch prediction status // Report branch prediction status
output logic BPPredWrongE, output logic BPPredWrongE,
output logic BPPredWrongM,
output logic BPPredDirWrongM, output logic BPPredDirWrongM,
output logic BTBPredPCWrongM, output logic BTBPredPCWrongM,
output logic RASPredPCWrongM, output logic RASPredPCWrongM,
@ -78,6 +82,8 @@ module bpred
logic SelBPPredF; logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF; logic [`XLEN-1:0] BPPredPCF;
logic BPPredWrongM;
@ -256,6 +262,11 @@ module bpred
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F)); mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate));
endmodule endmodule

10
pipelined/src/ifu/ifu.sv
View File

@ -305,19 +305,13 @@ module ifu (
// Branch and Jump Predictor // Branch and Jump Predictor
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
if (`BPRED_ENABLED) begin : bpred if (`BPRED_ENABLED) begin : bpred
logic BPPredWrongM;
bpred bpred(.clk, .reset, bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushD, .FlushE, .FlushM, .FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .PCBPWrongInvalidate,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate));
mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
end else begin : bpred end else begin : bpred
assign BPPredWrongE = PCSrcE; assign BPPredWrongE = PCSrcE;
assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;