From 565585b35abdd30ba7a9f4be8e91cb4e35dcc5f1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 19 Dec 2022 22:51:55 -0600
Subject: [PATCH] Moved more muxes inside bp.

---
 pipelined/src/ifu/bpred.sv | 13 ++++++++++++-
 pipelined/src/ifu/ifu.sv   | 10 ++--------
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
index 4e231282..5e55c994 100644
--- a/pipelined/src/ifu/bpred.sv
+++ b/pipelined/src/ifu/bpred.sv
@@ -43,8 +43,13 @@ module bpred
    input logic [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
    input logic [`XLEN-1:0]  PCPlus2or4F,
    output logic [`XLEN-1:0] PCNext0F,
+   output logic [`XLEN-1:0] PCCorrectE,
+   output logic [`XLEN-1:0]  PCBPWrongInvalidate, // The address of the currently executing instruction
+
    // Update Predictor
    input logic [`XLEN-1:0]  PCE, // The address of the currently executing instruction
+   input logic [`XLEN-1:0]  PCF, // The address of the currently executing instruction
+
    // 1 hot encoding
    // return, jump register, jump, branch
    // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
@@ -57,7 +62,6 @@ module bpred
    output logic [4:0]       InstrClassM,
    // Report branch prediction status
    output logic             BPPredWrongE,
-   output logic             BPPredWrongM, 
    output logic             BPPredDirWrongM,
    output logic             BTBPredPCWrongM,
    output logic             RASPredPCWrongM,
@@ -78,6 +82,8 @@ module bpred
   
   logic                     SelBPPredF;
   logic [`XLEN-1:0]         BPPredPCF;
+  logic                     BPPredWrongM;
+  
   
   
 
@@ -256,6 +262,11 @@ module bpred
 
 
   mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
+  mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
+  // Mux only required on instruction class miss prediction.
+  mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), 
+                                            .s(BPPredWrongM), .y(PCBPWrongInvalidate));
+  
   
 
 endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index d6640a6c..7b06c48b 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -305,19 +305,13 @@ module ifu (
   // Branch and Jump Predictor
   ////////////////////////////////////////////////////////////////////////////////////////////////
   if (`BPRED_ENABLED) begin : bpred
-    logic                        BPPredWrongM;
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, 
                 .FlushD, .FlushE, .FlushM,
-                .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE,
-                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, 
+                .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .PCBPWrongInvalidate,
+                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
                 .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
 
-    // Mux only required on instruction class miss prediction.
-    mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), 
-                                              .s(BPPredWrongM), .y(PCBPWrongInvalidate));
-    mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
-    
   end else begin : bpred
     assign BPPredWrongE = PCSrcE;
     assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;