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Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.

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This commit is contained in:
Ross Thompson 2022-08-29 13:01:24 -05:00
parent 40cf4a9ea9
commit 4d7b905806
4 changed files with 35 additions and 4 deletions
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4
pipelined/src/ebu/ahblite.sv
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@ -46,6 +46,8 @@ module ahblite (
input logic [1:0] IFUHTRANS,
input logic IFUBusRead,
input logic IFUTransComplete,
logic IFUHWRITE,
logic IFUHREADY,
output logic IFUBusInit,
output logic IFUBusAck,
@ -58,6 +60,8 @@ module ahblite (
input logic LSUBusRead,
input logic LSUBusWrite,
input logic LSUTransComplete,
logic LSUHWRITE,
logic LSUHREADY,
output logic LSUBusInit,
output logic LSUBusAck,

9
pipelined/src/ifu/ifu.sv
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@ -44,6 +44,8 @@ module ifu (
(* mark_debug = "true" *) output logic IFUStallF,
(* mark_debug = "true" *) output logic [2:0] IFUHBURST,
(* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
(* mark_debug = "true" *) output logic IFUHWRITE,
(* mark_debug = "true" *) input logic IFUHREADY,
(* mark_debug = "true" *) output logic IFUTransComplete,
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
// Execute
@ -248,12 +250,17 @@ module ifu (
assign IFUHADDR = PCPF;
flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0]));
/* -----\/----- EXCLUDED -----\/-----
busfsm #(LOGBWPL) busfsm(
.clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
.BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy,
.BusStall, .BusWrite(), .BusRead(IFUBusRead),
.HTRANS(IFUHTRANS), .BusCommitted());
-----/\----- EXCLUDED -----/\----- */
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
assign IFUHBURST = 3'b0;
assign IFUTransComplete = IFUBusAck;
assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;

12
pipelined/src/lsu/lsu.sv
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@ -56,7 +56,7 @@ module lsu (
// address and write data
input logic [`XLEN-1:0] IEUAdrE,
(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
(* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM,
(* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM,
output logic [`LLEN-1:0] ReadDataW,
// cpu privilege
input logic [1:0] PrivilegeModeW,
@ -78,6 +78,8 @@ module lsu (
(* mark_debug = "true" *) input logic LSUBusInit,
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA,
(* mark_debug = "true" *) input logic LSUHREADY,
(* mark_debug = "true" *) output logic LSUHWRITE,
(* mark_debug = "true" *) output logic [2:0] LSUHSIZE,
(* mark_debug = "true" *) output logic [2:0] LSUHBURST,
(* mark_debug = "true" *) output logic [1:0] LSUHTRANS,
@ -276,12 +278,18 @@ module lsu (
flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordM));
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
/* -----\/----- EXCLUDED -----\/-----
busfsm #(LOGBWPL) busfsm(
.clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
-----/\----- EXCLUDED -----/\----- */
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
.HWRITE(LSUHWRITE));
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
assign LSUHBURST = 3'b0;
assign LSUTransComplete = LSUBusAck;

14
pipelined/src/wally/wallypipelinedcore.sv
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@ -138,6 +138,8 @@ module wallypipelinedcore (
logic [2:0] IFUHBURST;
logic [1:0] IFUHTRANS;
logic IFUTransComplete;
logic IFUHWRITE;
logic IFUHREADY;
// AHB LSU interface
logic [`PA_BITS-1:0] LSUHADDR;
@ -145,6 +147,8 @@ module wallypipelinedcore (
logic LSUBusWrite;
logic LSUBusAck, LSUBusInit;
logic [`XLEN-1:0] LSUHWDATA;
logic LSUHWRITE;
logic LSUHREADY;
logic BPPredWrongE;
logic BPPredDirWrongM;
@ -166,6 +170,7 @@ module wallypipelinedcore (
logic InstrDAPageFaultF;
logic BigEndianM;
logic FCvtIntE;
ifu ifu(
.clk, .reset,
@ -174,6 +179,7 @@ module wallypipelinedcore (
// Fetch
.HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR,
.IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete,
.IFUHREADY, .IFUHWRITE,
.ICacheAccess, .ICacheMiss,
// Execute
@ -259,6 +265,7 @@ module wallypipelinedcore (
// connected to ahb (all stay the same)
.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
.HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete,
.LSUHWRITE, .LSUHREADY,
// connect to csr or privilege and stay the same.
.PrivilegeModeW, .BigEndianM, // connects to csr
@ -295,7 +302,10 @@ module wallypipelinedcore (
.IFUHTRANS,
.IFUTransComplete,
.IFUBusAck,
.IFUBusInit,
.IFUBusInit,
.IFUHWRITE,
.IFUHREADY,
// Signals from Data Cache
.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA,
.LSUHSIZE,
@ -304,6 +314,8 @@ module wallypipelinedcore (
.LSUTransComplete,
.LSUBusAck,
.LSUBusInit,
.LSUHWRITE,
.LSUHREADY,
.HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,