From 4d7b905806406b9725858076002163d24a5b125c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 29 Aug 2022 13:01:24 -0500 Subject: [PATCH] Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. --- pipelined/src/ebu/ahblite.sv | 4 ++++ pipelined/src/ifu/ifu.sv | 9 ++++++++- pipelined/src/lsu/lsu.sv | 12 ++++++++++-- pipelined/src/wally/wallypipelinedcore.sv | 14 +++++++++++++- 4 files changed, 35 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 674a9fdc..c27c0306 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -46,6 +46,8 @@ module ahblite ( input logic [1:0] IFUHTRANS, input logic IFUBusRead, input logic IFUTransComplete, + logic IFUHWRITE, + logic IFUHREADY, output logic IFUBusInit, output logic IFUBusAck, @@ -58,6 +60,8 @@ module ahblite ( input logic LSUBusRead, input logic LSUBusWrite, input logic LSUTransComplete, + logic LSUHWRITE, + logic LSUHREADY, output logic LSUBusInit, output logic LSUBusAck, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 377e5413..65e42a61 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -44,6 +44,8 @@ module ifu ( (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS, +(* mark_debug = "true" *) output logic IFUHWRITE, +(* mark_debug = "true" *) input logic IFUHREADY, (* mark_debug = "true" *) output logic IFUTransComplete, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute @@ -248,12 +250,17 @@ module ifu ( assign IFUHADDR = PCPF; flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0])); +/* -----\/----- EXCLUDED -----\/----- busfsm #(LOGBWPL) busfsm( .clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy, .BusStall, .BusWrite(), .BusRead(IFUBusRead), .HTRANS(IFUHTRANS), .BusCommitted()); - + -----/\----- EXCLUDED -----/\----- */ + + AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), + .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); + assign IFUHBURST = 3'b0; assign IFUTransComplete = IFUBusAck; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 713c793d..abd4afc5 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -56,7 +56,7 @@ module lsu ( // address and write data input logic [`XLEN-1:0] IEUAdrE, (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, - (* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM, + (* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM, output logic [`LLEN-1:0] ReadDataW, // cpu privilege input logic [1:0] PrivilegeModeW, @@ -78,6 +78,8 @@ module lsu ( (* mark_debug = "true" *) input logic LSUBusInit, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, + (* mark_debug = "true" *) input logic LSUHREADY, + (* mark_debug = "true" *) output logic LSUHWRITE, (* mark_debug = "true" *) output logic [2:0] LSUHSIZE, (* mark_debug = "true" *) output logic [2:0] LSUHBURST, (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, @@ -276,12 +278,18 @@ module lsu ( flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordM)); assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0]; +/* -----\/----- EXCLUDED -----\/----- busfsm #(LOGBWPL) busfsm( .clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM)); - + -----/\----- EXCLUDED -----/\----- */ + + AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), + .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), + .HWRITE(LSUHWRITE)); + assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign LSUHBURST = 3'b0; assign LSUTransComplete = LSUBusAck; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index f30d0056..c781d843 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -138,6 +138,8 @@ module wallypipelinedcore ( logic [2:0] IFUHBURST; logic [1:0] IFUHTRANS; logic IFUTransComplete; + logic IFUHWRITE; + logic IFUHREADY; // AHB LSU interface logic [`PA_BITS-1:0] LSUHADDR; @@ -145,6 +147,8 @@ module wallypipelinedcore ( logic LSUBusWrite; logic LSUBusAck, LSUBusInit; logic [`XLEN-1:0] LSUHWDATA; + logic LSUHWRITE; + logic LSUHREADY; logic BPPredWrongE; logic BPPredDirWrongM; @@ -166,6 +170,7 @@ module wallypipelinedcore ( logic InstrDAPageFaultF; logic BigEndianM; logic FCvtIntE; + ifu ifu( .clk, .reset, @@ -174,6 +179,7 @@ module wallypipelinedcore ( // Fetch .HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR, .IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete, + .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, // Execute @@ -259,6 +265,7 @@ module wallypipelinedcore ( // connected to ahb (all stay the same) .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, .HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, + .LSUHWRITE, .LSUHREADY, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -295,7 +302,10 @@ module wallypipelinedcore ( .IFUHTRANS, .IFUTransComplete, .IFUBusAck, - .IFUBusInit, + .IFUBusInit, + .IFUHWRITE, + .IFUHREADY, + // Signals from Data Cache .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA, .LSUHSIZE, @@ -304,6 +314,8 @@ module wallypipelinedcore ( .LSUTransComplete, .LSUBusAck, .LSUBusInit, + .LSUHWRITE, + .LSUHREADY, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,