forked from Github_Repos/cvw
Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache. instr addr correct got
This commit is contained in:
Ross Thompson
parent
c91436d3b7
commit
4322694f7a
@ -3,10 +3,13 @@ TARGET := $(TARGETDIR)/start
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ROOT := ..
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LIBRARY_DIRS :=
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LIBRARY_FILES :=
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LINK_FLAGS := -nostartfiles
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AFLAGS =-march=rv64ifd -W
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CFLAGS =-march=rv64ifd -mcmodel=medany
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MARCH :=-march=rv64ic
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MABI :=-mabi=lp64
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
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AFLAGS =$(MARCH) $(MABI) -march=rv64ic -mabi=lp64 -W
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CFLAGS =$(MARCH) $(MABI) -march=rv64ic -mabi=lp64 -mcmodel=medany
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AS=riscv64-unknown-elf-as
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CC=riscv64-unknown-elf-gcc
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AR=riscv64-unknown-elf-ar
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3
testsBP/mibench_qsort/LICENSE
Normal file
3
testsBP/mibench_qsort/LICENSE
Normal file
@ -0,0 +1,3 @@
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Matt wrote this using STL.
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It is GPL'ed.
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19
testsBP/mibench_qsort/Makefile
Normal file
19
testsBP/mibench_qsort/Makefile
Normal file
@ -0,0 +1,19 @@
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TARGETDIR := qsort
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TARGET := $(TARGETDIR)/$(TARGETDIR).elf
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ROOT := ..
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LIBRARY_DIRS := ${ROOT}/crt0
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LIBRARY_FILES := crt0
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MARCH :=-march=rv64ic
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MABI :=-mabi=lp64
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
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CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
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CC=riscv64-unknown-elf-gcc
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DA=riscv64-unknown-elf-objdump -d
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include $(ROOT)/makefile.inc
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10038
testsBP/mibench_qsort/qsort_small.c
Normal file
10038
testsBP/mibench_qsort/qsort_small.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,9 +3,13 @@ TARGET := $(TARGETDIR)/$(TARGETDIR).elf
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ROOT := ..
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LIBRARY_DIRS := ${ROOT}/crt0
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LIBRARY_FILES := crt0
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LINK_FLAGS := -nostartfiles -Wl,-Map=$(TARGET).map
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CFLAGS =-march=rv64ifd -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
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MARCH :=-march=rv64ic
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MABI :=-mabi=lp64
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
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CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
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CC=riscv64-unknown-elf-gcc
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DA=riscv64-unknown-elf-objdump -d
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@ -3,9 +3,12 @@ TARGET := $(TARGETDIR)/$(TARGETDIR).elf
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ROOT := ..
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LIBRARY_DIRS := ${ROOT}/crt0
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LIBRARY_FILES := crt0
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LINK_FLAGS := -nostartfiles -Wl,-Map=$(TARGET).map
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CFLAGS =-march=rv64ifd -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
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MARCH :=-march=rv64ic
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MABI :=-mabi=lp64
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
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CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
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CC=riscv64-unknown-elf-gcc
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DA=riscv64-unknown-elf-objdump -d
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19
testsBP/simple/lbu_test.s
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19
testsBP/simple/lbu_test.s
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@ -0,0 +1,19 @@
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.section .text
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.global lbu_test
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.type lbu_test, @function
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lbu_test:
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li t0, 0x80000
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lbu t1, 0(t0)
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pass:
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li a0, 0
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done:
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ret
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fail:
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li a0, -1
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j done
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@ -18,11 +18,7 @@ my $maxaddress = 0;
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STDOUT->autoflush(1);
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# *** Ross Thompson I think there is a bug here needs to be +1
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<<<<<<< HEAD
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print ("Processing $#ARGV memfiles: \n");
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=======
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print ("Processing $#ARGV memfiles: ");
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>>>>>>> icache_bp_bug
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my $frac = $#ARGV/10;
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for(my $i=0; $i<=$#ARGV; $i++) {
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if ($i < 10 || $i % $frac == 0) { print ("$i ") };
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@ -59,29 +59,30 @@ add wave -noupdate -group Bpred -expand -group direction -group other /testbench
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCSrcE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group {bp wrong} -divider pcs
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD
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add wave -noupdate -group Bpred -expand -group BTB -divider Update
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
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add wave -noupdate -group Bpred -expand -group BTB -divider Lookup
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/InstrClass
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
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add wave -noupdate -group Bpred -group BTB -divider Update
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
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add wave -noupdate -group Bpred -group BTB -divider Lookup
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/InstrClass
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pop
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/push
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pushPC
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrD
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrQ
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/memory
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add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/popPC
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pop
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/push
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pushPC
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrD
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrQ
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/memory
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add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/popPC
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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@ -94,25 +95,26 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/ic/DelaySideF
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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@ -186,8 +188,8 @@ add wave -noupdate /testbench/dut/imem/InstrF
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add wave -noupdate /testbench/dut/InstrF
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add wave -noupdate /testbench/dut/InstrF
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add wave -noupdate -divider {New Divider}
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add wave -noupdate /testbench/dut/hart/ifu/ic/InDataF
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add wave -noupdate /testbench/dut/hart/ifu/InstrInF
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add wave -noupdate /testbench/dut/hart/ifu/rd2
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add wave -noupdate /testbench/dut/hart/InstrRData
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add wave -noupdate /testbench/dut/hart/rd2
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add wave -noupdate /testbench/dut/hart/ebu/InstrRData
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@ -217,9 +219,10 @@ add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR
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add wave -noupdate /testbench/dut/uncore/dtim/RAM
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add wave -noupdate /testbench/dut/uncore/dtim/HREADTim
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add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0
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add wave -noupdate /testbench/dut/uncore/dtim/HRESETn
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 7} {15047768 ns} 0} {{Cursor 2} {34763538 ns} 0} {{Cursor 3} {15046271 ns} 0} {{Cursor 4} {15047307 ns} 0}
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quietly wave cursor active 1
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WaveRestoreCursors {{Cursor 7} {10896277 ns} 1} {{Cursor 9} {10896453 ns} 0} {{wrong instruction} {10895117 ns} 0}
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quietly wave cursor active 3
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 229
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configure wave -justifyvalue left
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@ -234,4 +237,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {15047734 ns} {15047902 ns}
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WaveRestoreZoom {10895029 ns} {10895205 ns}
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@ -37,6 +37,9 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
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output logic HRESPTim, HREADYTim
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);
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localparam integer MemStartAddr = BASE>>(1+`XLEN/32);
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localparam integer MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
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logic [31:0] HWADDR, A;
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logic [`XLEN-1:0] HREADTim0;
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@ -48,6 +51,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
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logic memread, memwrite;
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logic [3:0] busycount;
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assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
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// *** this seems like a weird way to use reset
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@ -82,6 +86,16 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
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assign risingHREADYTim = HREADYTim & ~prevHREADYTim;
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// Model memory read and write
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/* -----\/----- EXCLUDED -----\/-----
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integer index;
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initial begin
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for(index = MemStartAddr; index < MemEndAddr; index = index + 1) begin
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RAM[index] <= {`XLEN{1'b0}};
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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generate
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if (`XLEN == 64) begin
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always_ff @(posedge HCLK) begin
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@ -386,17 +386,24 @@ string tests32i[] = {
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InstrEName, InstrMName, InstrWName);
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// initialize tests
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localparam integer MemStartAddr = `TIMBASE>>(1+`XLEN/32);
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localparam integer MemEndAddr = (`TIMRANGE+`TIMBASE)>>1+(`XLEN/32);
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initial
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begin
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test = 0;
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totalerrors = 0;
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testadr = 0;
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// fill memory with defined values to reduce Xs in simulation
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// Quick note the memory will need to be initialized. The C library does not
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// guarantee the initialized reads. For example a strcmp can read 6 byte
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// strings, but uses a load double to read them in. If the last 2 bytes are
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// not initialized the compare results in an 'x' which propagates through
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// the design.
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if (`XLEN == 32) meminit = 32'hFEDC0123;
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else meminit = 64'hFEDCBA9876543210;
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for (i=0; i<=65535; i = i+1) begin
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//dut.imem.RAM[i] = meminit;
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// dut.uncore.RAM[i] = meminit;
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for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
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dut.uncore.dtim.RAM[i] = meminit;
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end
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// read test vectors into memory
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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Loading…
Reference in New Issue
Block a user