From 3e57c899a2f13b423bcebd8db6336fa5c5f84792 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 17:24:59 -0500 Subject: [PATCH] Partially working changes to support uncached memory access. Not sure what CommitedM is. --- wally-pipelined/regression/wave.do | 77 ++++++++++--------- wally-pipelined/src/cache/dcache.sv | 47 ++++++++--- wally-pipelined/src/ifu/ifu.sv | 3 + wally-pipelined/src/lsu/lsu.sv | 25 ++++-- wally-pipelined/src/mmu/mmu.sv | 2 +- .../src/wally/wallypipelinedhart.sv | 5 +- .../testbench/testbench-imperas.sv | 1 - 7 files changed, 103 insertions(+), 57 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 807eacba..f53880fd 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -239,22 +239,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -272,8 +272,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM @@ -290,6 +288,15 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -312,20 +319,20 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR @@ -394,8 +401,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1979564 ns} {1979828 ns} +WaveRestoreZoom {4642 ns} {4816 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3bcd4719..f33385df 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -48,7 +48,7 @@ module dcache // inputs from TLB and PMA/P input logic FaultM, input logic DTLBMissM, - input logic UncachedM, + input logic CacheableM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -114,6 +114,8 @@ module dcache logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; + logic [OFFSETLEN-1:0] BasePAdrOffsetM; + logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; @@ -224,7 +226,7 @@ module dcache // variable input mux assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - assign HWDATA = VictimReadDataBlockSetsM[FetchCount]; + assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; // finally swr // *** BUG fix HSIZED? why was it this way? @@ -271,14 +273,17 @@ module dcache // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .s(AHBWrite), + .s(AHBWrite & CacheableM), .y(BasePAdrM)); + + assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; + assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; + assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; + assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM; end endgenerate @@ -339,6 +344,8 @@ module dcache STATE_PTW_MISS_READ_SRAM, STATE_UNCACHED_WDV, STATE_UNCACHED_DONE, + STATE_UNCACHED_WRITE, + STATE_UNCACHED_WRITE_DONE, STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -398,7 +405,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; @@ -406,7 +413,7 @@ module dcache else NextState = STATE_READY; end // read hit valid cached - else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -414,7 +421,7 @@ module dcache else NextState = STATE_READY; end // write hit valid cached - else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; @@ -424,11 +431,19 @@ module dcache else NextState = STATE_READY; end // read or write miss valid cached - else if((|MemRWM) & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end + // uncached write + else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_WRITE; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBWrite = 1'b1; + + end // fault else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; @@ -529,6 +544,20 @@ module dcache if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end + + STATE_UNCACHED_WRITE : begin + DCacheStall = 1'b1; + AHBWrite = 1'b1; + if(AHBAck) begin + NextState = STATE_UNCACHED_WRITE_DONE; + end else begin + NextState = STATE_UNCACHED_WRITE; + end + end + + STATE_UNCACHED_WRITE_DONE: begin + NextState = STATE_READY; + end default: begin end endcase diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index e306efa4..af5686d5 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -136,6 +136,9 @@ module ifu ( .LoadAccessFaultM(), .StoreAccessFaultM(), .DisableTranslation(1'b0), + .Cacheable(), + .Idempotent(), + .AtomicAllowed(), .*); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 432645f7..9ed573a9 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -62,12 +62,13 @@ module lsu // connect to ahb input logic CommitM, // should this be generated in the abh interface? - output logic [`PA_BITS-1:0] DCtoAHBPAdrM, // to ahb + output logic [`PA_BITS-1:0] DCtoAHBPAdrM, output logic DCtoAHBReadM, output logic DCtoAHBWriteM, - input logic DCfromAHBAck, // from ahb - input logic [`XLEN-1:0] DCfromAHBReadData, // from ahb - output logic [`XLEN-1:0] DCtoAHBWriteData, // to ahb + input logic DCfromAHBAck, + input logic [`XLEN-1:0] DCfromAHBReadData, + output logic [`XLEN-1:0] DCtoAHBWriteData, + output logic [2:0] DCtoAHBSizeM, // mmu management @@ -140,8 +141,8 @@ module lsu logic HPTWReady; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. logic DCacheStall; - - + + logic CacheableM; pagetablewalker pagetablewalker( .clk(clk), @@ -223,9 +224,19 @@ module lsu .SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), + .Cacheable(CacheableM), + .Idempotent(), + .AtomicAllowed(), // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + + generate + if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache; + else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache; + endgenerate; + + // Specify which type of page fault is occurring assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1]; assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0]; @@ -310,7 +321,7 @@ module lsu .DCacheStall(DCacheStall), .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. .DTLBMissM(DTLBMissM), - .UncachedM(1'b0), // ***connect to PMA + .CacheableM(CacheableM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 9372f473..d71cbe81 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -60,6 +60,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, + output logic Cacheable, Idempotent, AtomicAllowed, // Faults output logic TLBPageFault, @@ -76,7 +77,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries ); logic PMPSquashBusAccess, PMASquashBusAccess; - logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here. // Translation lookaside buffer logic PMAInstrAccessFaultF, PMPInstrAccessFaultF; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index f094df60..55c8959f 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -196,6 +196,7 @@ module wallypipelinedhart .DCfromAHBAck(DCfromAHBAck), .DCfromAHBReadData(DCfromAHBReadData), .DCtoAHBWriteData(DCtoAHBWriteData), + .DCtoAHBSizeM(DCtoAHBSizeM), // connect to csr or privilege and stay the same. .PrivilegeModeW(PrivilegeModeW), // connects to csr @@ -231,10 +232,6 @@ module wallypipelinedhart .LSUStall(DCacheStall)); // change to DCacheStall - generate - if (`XLEN == 32) assign DCtoAHBSizeM = 3'b010; - else assign DCtoAHBSizeM = 3'b011; - endgenerate; ahblite ebu(// IFU connections diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 25cb1ef6..654c34fb 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -547,7 +547,6 @@ string tests32f[] = '{ if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - tests = {tests64i, tests}; end //tests = {tests64a, tests}; end else begin // RV32