forked from Github_Repos/cvw
Hacky fix to prevent ITLBMissF and TrapM bug.
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parent
70e207e010
commit
396f697d2f
3
pipelined/src/cache/cache.sv
vendored
3
pipelined/src/cache/cache.sv
vendored
@ -51,6 +51,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
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// lsu control
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// lsu control
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input logic IgnoreRequestTLB,
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input logic IgnoreRequestTLB,
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input logic IgnoreRequestTrapM,
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input logic IgnoreRequestTrapM,
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input logic TrapM,
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input logic Cacheable,
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input logic Cacheable,
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// Bus fsm interface
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// Bus fsm interface
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output logic CacheFetchLine,
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output logic CacheFetchLine,
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@ -195,7 +196,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
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assign CacheRW = Cacheable ? RW : 2'b00;
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assign CacheRW = Cacheable ? RW : 2'b00;
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assign CacheAtomic = Cacheable ? Atomic : 2'b00;
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assign CacheAtomic = Cacheable ? Atomic : 2'b00;
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cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
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cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
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.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM,
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.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearValid, .ClearDirty, .SetDirty,
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.ClearValid, .ClearDirty, .SetDirty,
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3
pipelined/src/cache/cachefsm.sv
vendored
3
pipelined/src/cache/cachefsm.sv
vendored
@ -42,6 +42,7 @@ module cachefsm
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// interlock fsm
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// interlock fsm
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input logic IgnoreRequestTLB,
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input logic IgnoreRequestTLB,
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input logic IgnoreRequestTrapM,
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input logic IgnoreRequestTrapM,
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input logic TrapM,
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// Bus inputs
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// Bus inputs
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input logic CacheBusAck,
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input logic CacheBusAck,
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// dcache internals
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// dcache internals
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@ -217,7 +218,7 @@ module cachefsm
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(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
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(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
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// **** can this be simplified?
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// **** can this be simplified?
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assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
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assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
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// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
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// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
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(CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
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(CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
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(CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
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(CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
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@ -212,7 +212,7 @@ module ifu (
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0),
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icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0),
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.CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
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.CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheFetchLine(ICacheFetchLine),
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.CacheFetchLine(ICacheFetchLine),
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@ -232,7 +232,7 @@ module lsu (
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.ByteMask(ByteMaskM), .WordCount,
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.ByteMask(ByteMaskM), .WordCount,
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.FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
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.FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM),
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.IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
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.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
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.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
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.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
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.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
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