diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 067bfb74..ed7a1272 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -51,6 +51,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
    // lsu control
   input logic                 IgnoreRequestTLB,
   input logic                 IgnoreRequestTrapM, 
+  input logic                 TrapM,
   input logic                 Cacheable,
    // Bus fsm interface
   output logic                CacheFetchLine,
@@ -195,7 +196,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   assign CacheRW = Cacheable ? RW : 2'b00;
   assign CacheAtomic = Cacheable ? Atomic : 2'b00;
   cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, 
-		.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM,
+		.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM,
  		.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, 
 		.CacheMiss, .CacheAccess, .SelAdr, 
 		.ClearValid, .ClearDirty, .SetDirty,
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index b98ecf7d..857884c4 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -32,49 +32,50 @@
 
 module cachefsm
   (input logic clk,
-   input logic       reset,
+   input logic 		 reset,
    // inputs from IEU
    input logic [1:0] CacheRW,
    input logic [1:0] CacheAtomic,
-   input logic       FlushCache,
+   input logic 		 FlushCache,
    // hazard inputs
-   input logic       CPUBusy,
+   input logic 		 CPUBusy,
    // interlock fsm
-   input logic       IgnoreRequestTLB,
-   input logic       IgnoreRequestTrapM, 
+   input logic 		 IgnoreRequestTLB,
+   input logic 		 IgnoreRequestTrapM,
+   input logic       TrapM,
    // Bus inputs
-   input logic       CacheBusAck,
+   input logic 		 CacheBusAck,
    // dcache internals
-   input logic       CacheHit,
-   input logic       VictimDirty,
-   input logic       FlushAdrFlag,
-   input logic       FlushWayFlag, 
+   input logic 		 CacheHit,
+   input logic 		 VictimDirty,
+   input logic 		 FlushAdrFlag,
+   input logic 		 FlushWayFlag, 
   
    // hazard outputs
-   output logic      CacheStall,
+   output logic 	 CacheStall,
    // counter outputs
-   output logic      CacheMiss,
-   output logic      CacheAccess,
+   output logic 	 CacheMiss,
+   output logic 	 CacheAccess,
    // Bus outputs
-   output logic      CacheCommitted,
-   output logic      CacheWriteLine,
-   output logic      CacheFetchLine,
+   output logic 	 CacheCommitted,
+   output logic 	 CacheWriteLine,
+   output logic 	 CacheFetchLine,
 
    // dcache internals
-   output logic      SelAdr,
-   output logic      ClearValid,
-   output logic      ClearDirty,
-   output logic      SetDirty,
-   output logic      SetValid,
-   output logic      SelEvict,
-   output logic      LRUWriteEn,
-   output logic      SelFlush,
-   output logic      FlushAdrCntEn,
-   output logic      FlushWayCntEn, 
-   output logic      FlushAdrCntRst,
-   output logic      FlushWayCntRst,
-   output logic      save,
-   output logic      restore);
+   output logic 	 SelAdr,
+   output logic 	 ClearValid,
+   output logic 	 ClearDirty,
+   output logic 	 SetDirty,
+   output logic 	 SetValid,
+   output logic 	 SelEvict,
+   output logic 	 LRUWriteEn,
+   output logic 	 SelFlush,
+   output logic 	 FlushAdrCntEn,
+   output logic 	 FlushWayCntEn, 
+   output logic 	 FlushAdrCntRst,
+   output logic 	 FlushWayCntRst,
+   output logic 	 save,
+   output logic 	 restore);
   
   logic               resetDelay;
   logic               AMO;
@@ -217,7 +218,7 @@ module cachefsm
                  (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
 
   // **** can this be simplified?
-  assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
+  assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
                   // use the raw requests as we don't want IgnoreRequestTrapM in the critical path
                   (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
                   (CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 0e8c2f79..05b0aa51 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -212,7 +212,7 @@ module ifu (
       cache #(.LINELEN(`ICACHE_LINELENINBITS),
               .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
               .NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
-      icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0),
+      icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0),
              .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
              .CacheFetchLine(ICacheFetchLine),
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index d5e5b2b3..027370ce 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -232,7 +232,7 @@ module lsu (
         .ByteMask(ByteMaskM), .WordCount,
         .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
-        .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), 
+        .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM), 
         .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), 
         .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), 
         .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));