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Remove unused signals

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This commit is contained in:
David Harris 2023-01-07 06:26:29 -08:00
parent dc526c92bd
commit 33c910f952
16 changed files with 27 additions and 62 deletions
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3
bin/vclean.pl
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@ -35,7 +35,8 @@ sub clean {
}
# print("Signals: @allsigs\n");
foreach my $sig (@allsigs) {
# print("Searching for $sig\n");
if ($sig eq "") { last }; # skip empty signals
# print("Searching for '$sig'\n");
my $hits = `grep -c $sig $fname`;
# print(" Signal $sig appears $hits times\n");
if ($hits < 2) {

6
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -68,7 +68,7 @@ module fdivsqrt(
logic DivStartE; // Enable signal for flops during stall
// Integer div/rem signals
logic BZeroE, BZeroM; // Denominator is zero
logic BZeroM; // Denominator is zero
logic MDUM; // Integer operation
logic [`DIVBLEN:0] nE, nM, mM; // Shift amounts
logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
@ -81,7 +81,7 @@ module fdivsqrt(
.QeM, .X, .DPreproc,
// Int-specific
.ForwardedSrcAE, .ForwardedSrcBE, .MDUE, .W64E, .ISpecialCaseE,
.BZeroE, .nE, .BZeroM, .nM, .mM, .AM,
.nE, .BZeroM, .nM, .mM, .AM,
.MDUM, .W64M, .NegQuotM, .ALTBM, .AsM);
fdivsqrtfsm fdivsqrtfsm( // FSM
@ -89,7 +89,7 @@ module fdivsqrt(
.FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM,
.FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM,
// Int-specific
.IDivStartE, .BZeroE, .ISpecialCaseE, .nE, .MDUE);
.IDivStartE, .ISpecialCaseE, .nE, .MDUE);
fdivsqrtiter fdivsqrtiter( // CSA Iterator
.clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc,

1
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -36,7 +36,6 @@ module fdivsqrtfsm(
input logic [`FMTBITS-1:0] FmtE,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic BZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic XsE,

4
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -48,7 +48,7 @@ module fdivsqrtpreproc (
output logic ISpecialCaseE,
output logic [`DIVBLEN:0] nE, nM, mM,
output logic NegQuotM, ALTBM, MDUM, W64M,
output logic AsM, BZeroM, BZeroE,
output logic AsM, BZeroM,
output logic [`XLEN-1:0] AM
);
@ -59,7 +59,7 @@ module fdivsqrtpreproc (
logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator
logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs
logic NumerZeroE; // Numerator is zero (X or A)
logic AZeroE; // A is Zero for integer division
logic AZeroE, BZeroE; // A or B is Zero for integer division
if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
logic signedDiv, NegQuotE;

1
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
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@ -37,7 +37,6 @@ module fdivsqrtqsel2 (
logic [3:0] p, g;
logic magnitude, sign;
logic pos, neg;
// The quotient selection logic is presented for simplicity, not
// for efficiency. You can probably optimize your logic to

1
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
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@ -40,7 +40,6 @@ module fdivsqrtqsel4cmp (
logic [6:0] Wmsbs;
logic [7:0] PreWmsbs;
logic [2:0] A;
logic [3:0] udigitsel, udigitswap;
assign PreWmsbs = WCmsbs + WSmsbs;
assign Wmsbs = PreWmsbs[7:1];

1
pipelined/src/fpu/fma/fmaadd.sv
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@ -46,7 +46,6 @@ module fmaadd(
output logic [3*`NF+3:0] Sm // the positive sum
);
logic [3*`NF+3:0] PreSum, NegPreSum; // possibly negitive sum
logic [3*`NF+5:0] PreSumdebug, NegPreSumdebug; // possibly negitive sum
logic NegSum; // was the sum negitive
logic NegSumdebug; // was the sum negitive

16
pipelined/src/fpu/fpu.sv
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@ -99,9 +99,9 @@ module fpu (
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
logic XSubnormE, ZSubnormE, ZSubnormM; // is the input Subnormalized
logic XSubnormE; // is the input Subnormalized
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
logic XZeroM, YZeroM; // is the input zero - memory stage
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
logic XExpMaxE; // is the exponent all ones (max value)
@ -239,7 +239,7 @@ module fpu (
unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE),
.Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
.XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE),
.YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), .ZSubnorm(ZSubnormE),
.YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE),
.XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE),
.ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE));
@ -345,9 +345,9 @@ module fpu (
flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
flopenr #(15) EMFpReg5 (clk, reset, ~StallUnpackedM,
{XsE, YsE, XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE, ZSubnormE},
{XsM, YsM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZSubnormM});
flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM,
{XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
{XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);
flopenrc #(3*`NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
@ -372,9 +372,9 @@ module fpu (
assign FpLoadStoreM = FResSelM[1];
postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM),
.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
.ZSubnorm(ZSubnormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
.FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
.CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM),
.CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));

1
pipelined/src/fpu/postproc/divshiftcalc.sv
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@ -32,7 +32,6 @@
module divshiftcalc(
input logic [`DIVb:0] DivQm,
input logic Sqrt,
input logic [`NE+1:0] DivQe,
output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt,
output logic [`NORMSHIFTSZ-1:0] DivShiftIn,

5
pipelined/src/fpu/postproc/postprocess.sv
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@ -37,11 +37,10 @@ module postprocess (
input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
input logic XZero, YZero, ZZero, // inputs are zero
input logic XZero, YZero, // inputs are zero
input logic XInf, YInf, ZInf, // inputs are infinity
input logic XNaN, YNaN, ZNaN, // inputs are NaN
input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
input logic ZSubnorm, // is the original precision Subnormalized
input logic [1:0] PostProcSel, // select result to be written to fp register
//fma signals
input logic FmaAs, // the modified Z sign - depends on instruction
@ -146,7 +145,7 @@ module postprocess (
.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
fmashiftcalc fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
.FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
divshiftcalc divshiftcalc(.Sqrt, .DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
divshiftcalc divshiftcalc(.DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
always_comb
case(PostProcSel)

3
pipelined/src/fpu/unpack.sv
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@ -38,7 +38,7 @@ module unpack (
output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
output logic XSubnorm, ZSubnorm, // is XYZ Subnormalized
output logic XSubnorm, // is X Subnormalized
output logic XZero, YZero, ZZero, // is XYZ zero
output logic XInf, YInf, ZInf, // is XYZ infinity
output logic XExpMax // does X have the maximum exponent (NaN or Inf)
@ -61,5 +61,4 @@ module unpack (
.Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
// is the input Subnormalized
assign XSubnorm = ~XExpNonZero & ~XFracZero;
assign ZSubnorm = ~ZExpNonZero & ~ZFracZero;
endmodule

15
pipelined/src/uncore/sdc/SDCcounter.sv
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@ -41,20 +41,9 @@ module SDCcounter #(parameter integer WIDTH=32)
input logic reset);
logic [WIDTH-1:0] NextCount;
logic [WIDTH-1:0] count_q;
logic [WIDTH-1:0] CountP1;
flopenr #(WIDTH) reg1(.clk,
.reset,
.en(Enable | Load),
.d(NextCount),
.q(CountOut));
assign CountP1 = CountOut + 1'b1;
// mux between load and P1
assign NextCount = Load ? CountIn : CountP1;
assign NextCount = Load ? CountIn : (CountOut + 1'b1);
flopenr #(WIDTH) reg1(clk, reset, Enable | Load, NextCount, CountOut);
endmodule

5
pipelined/src/uncore/sdc/sd_top.sv
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@ -178,7 +178,6 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
logic [1:0] w_TX_SOURCE_SELECT;
logic w_CMD_TX_IS_CMD55_RST;
logic w_CMD_TX_IS_CMD55_EN;
//logic w_CMD_RX;
logic w_RX_SIPO48_RST, w_RX_SIPO48_EN;
(* mark_debug = "true" *)logic [39:8] r_RESPONSE_CONTENT;
(* mark_debug = "true" *)logic [45:40] r_RESPONSE_INDEX;
@ -208,7 +207,6 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
logic w_BUSY_RST, w_BUSY_EN;
logic w_NIBO_EN;
logic w_DATA_CRC16_GOOD;
logic w_VALID_BLOCK_D, w_VALID_BLOCK_EN, w_VALID_WIDE_D, w_VALID_WIDE_EN;
logic [22:0] w_DAT_TIMER_IN;
logic [22:0] r_DAT_TIMER_OUT;
logic [10:0] r_DAT_COUNTER_OUT;
@ -237,7 +235,6 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
logic [2:0] r_command_index_is_55_history ; // [0] is live index, [1] is currently saved index, [2] is index of previous command
logic r_previous_command_index_was_55_q; // is index of previous command 55, wired to r_command_index_is_55_history[2]
logic r_ACMD_Q; // if the previous command sent to the SD card successfully had index 55, then the SD card thinks the current command is ACMD
logic [4095:0] r_block_data ; // data block from CMD17
// TX
logic [45:8] w_command_content; // first 40 bits of command packet
@ -245,7 +242,6 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
logic w_tx_tail_Q; // transmission of last part of command packet
logic [7:0] r_command_tail; // last 8 bits of command packet
logic [6:0] r_TX_CRC7;
//logic w_TX_Q:= '0'; // actual transmission when tx is enabled
// RX
logic [47:0] r_RX_RESPONSE;
@ -264,7 +260,6 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
logic w_G_CLK_SD_EN;
logic r_CLK_SD, r_G_CLK_SD; // clocks
logic r_G_CLK_SD_n;
logic [15:0] r_CLK_FSM_RST ; // a_rst logic delayed by one 1.2 GHz period
logic w_SD_CLK_SELECTED;

11
pipelined/src/uncore/sdc/up_down_counter.sv
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@ -41,20 +41,11 @@ module up_down_counter #(parameter integer WIDTH=32)
input logic reset);
logic [WIDTH-1:0] NextCount;
logic [WIDTH-1:0] count_q;
logic [WIDTH-1:0] CountP1;
flopenr #(WIDTH) reg1(.clk,
.reset,
.en(Enable | Load),
.d(NextCount),
.q(CountOut));
assign CountP1 = UpDown ? CountOut + 1'b1 : CountOut - 1'b1;
// mux between load and P1
assign NextCount = Load ? CountIn : CountP1;
flopenr #(WIDTH) reg1(clk, reset, Enable | Load, NextCount, CountOut);
endmodule

2
pipelined/src/uncore/uncore.sv
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@ -31,8 +31,6 @@
`include "wally-config.vh"
// *** need idiom to map onto cache RAM with byte writes
// *** and use memread signal to reduce power when reads aren't needed
module uncore (
// AHB Bus Interface
input logic HCLK, HRESETn,

4
pipelined/src/wally/wallypipelinedcore.sv
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@ -51,7 +51,6 @@ module wallypipelinedcore (
output logic HMASTLOCK
);
// logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW;
logic FlushD, FlushE, FlushM, FlushW;
logic RetM;
@ -66,7 +65,7 @@ module wallypipelinedcore (
logic [2:0] Funct3E;
logic [31:0] InstrD;
(* mark_debug = "true" *) logic [31:0] InstrM;
logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
logic [`XLEN-1:0] PCF, PCE, PCLinkE;
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
@ -97,7 +96,6 @@ module wallypipelinedcore (
logic FRegWriteM;
logic FCvtIntStallD;
logic FpLoadStoreM;
logic [1:0] FResSelW;
logic [4:0] SetFflagsM;
logic [`XLEN-1:0] FPIntDivResultW;