forked from Github_Repos/cvw
172 lines
8.0 KiB
Systemverilog
172 lines
8.0 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtpreproc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtpreproc (
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input logic clk,
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input logic IFDivStartE,
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input logic [`NF:0] Xm, Ym,
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input logic [`NE-1:0] Xe, Ye,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic XZeroE,
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input logic [2:0] Funct3E,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb+3:0] X,
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output logic [`DIVb-1:0] DPreproc,
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// Int-specific
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic MDUE, W64E,
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output logic ISpecialCaseE,
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output logic [`DIVBLEN:0] nE, nM, mM,
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output logic NegQuotM, ALTBM, MDUM, W64M,
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output logic AsM, BZeroM,
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output logic [`XLEN-1:0] AM
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);
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logic [`DIVb-1:0] XPreproc;
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logic [`DIVb:0] PreSqrtX;
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logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator
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logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs
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logic NumerZeroE; // Numerator is zero (X or A)
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
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logic signedDiv, NegQuotE;
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logic AsBit, BsBit, AsE, BsE, ALTBE;
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logic [`XLEN-1:0] AE, BE, PosA, PosB;
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logic [`DIVBLEN:0] ZeroDiff, p;
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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assign signedDiv = ~Funct3E[0];
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assign NegQuotE = AsE ^ BsE; // Quotient is negative
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// Source handling
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if (`XLEN==64) begin // 64-bit, supports W64
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mux2 #(1) azeromux(~(|ForwardedSrcAE), ~(|ForwardedSrcAE[31:0]), W64E, AZeroE);
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mux2 #(1) bzeromux(~(|ForwardedSrcBE), ~(|ForwardedSrcBE[31:0]), W64E, BZeroE);
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mux2 #(1) abitmux(ForwardedSrcAE[63], ForwardedSrcAE[31], W64E, AsBit);
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mux2 #(1) bbitmux(ForwardedSrcBE[63], ForwardedSrcBE[31], W64E, BsBit);
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mux2 #(64) amux(ForwardedSrcAE, {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]}, W64E, AE);
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mux2 #(64) bmux(ForwardedSrcBE, {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]}, W64E, BE);
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assign AsE = signedDiv & AsBit;
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assign BsE = signedDiv & BsBit;
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end else begin // 32 bits only
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assign AsE = signedDiv & ForwardedSrcAE[31];
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assign BsE = signedDiv & ForwardedSrcBE[31];
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assign AE = ForwardedSrcAE;
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assign BE = ForwardedSrcBE;
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assign AZeroE = ~(|ForwardedSrcAE);
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assign BZeroE = ~(|ForwardedSrcBE);
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end
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// Force integer inputs to be postiive
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mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
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mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
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// Select integer or floating point inputs
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mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, MDUE, IFNormLenX);
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mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, MDUE, IFNormLenD);
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// calculate number of fractional bits p
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assign ZeroDiff = mE - ell; // Difference in number of leading zeros
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assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B (A has more leading zeros)
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mux2 #(`DIVBLEN+1) pmux(ZeroDiff, {(`DIVBLEN+1){1'b0}}, ALTBE, p); // *** is there a more graceful way to write these constants
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// Integer special cases (terminate immediately)
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assign ISpecialCaseE = BZeroE | ALTBE;
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/* verilator lint_off WIDTH */
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// calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
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if (`LOGRK > 0) begin // more than 1 bit per cycle
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logic [`LOGRK-1:0] IntTrunc, RightShiftX;
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logic [`DIVBLEN:0] TotalIntBits, IntSteps;
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assign TotalIntBits = `LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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assign IntTrunc = TotalIntBits % `RK; // Truncation check for ceiling operator
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assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc; // Number of steps for int div
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assign nE = (IntSteps * `DIVCOPIES) - 1; // Fractional digits
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assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK); // Right shift amount
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps
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end else begin // radix 2 1 copy doesn't require shifting
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assign nE = p;
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assign DivXShifted = DivX;
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end
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/* verilator lint_on WIDTH */
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// Selet integer or floating-point operands
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mux2 #(1) numzmux(XZeroE, AZeroE, MDUE, NumerZeroE);
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mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, MDUE, X);
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// pipeline registers
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flopen #(1) mdureg(clk, IFDivStartE, MDUE, MDUM);
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
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end else begin // Int not supported
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assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFNormLenD = {Ym, {(`DIVb-`NF-1){1'b0}}};
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assign NumerZeroE = XZeroE;
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assign X = PreShiftX;
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end
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// count leading zeros for Subnorm FP and to normalize integer inputs
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lzc #(`DIVb) lzcX (IFNormLenX, ell);
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lzc #(`DIVb) lzcY (IFNormLenD, mE);
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// Normalization shift
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1});
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assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for nonzero inputs) and conditionally shift left by one to avoid sqrt(2)
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mux2 #(`DIVb+1) sqrtxmux({~NumerZeroE, XPreproc}, {1'b0, ~NumerZeroE, XPreproc[`DIVb-1:1]}, (Xe[0]^ell[0]), PreSqrtX);
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assign DivX = {3'b000, ~NumerZeroE, XPreproc};
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// Sqrt is initialized on step one as R(X-1), so depends on Radix
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if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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mux2 #(`DIVb+4) prexmux(DivX, SqrtX, Sqrt, PreShiftX);
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// Floating-point exponent
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fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
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flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
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endmodule
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