From 0f2ac0cb2447ad547b733304165b6774497190dd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 14:54:57 -0600 Subject: [PATCH 01/12] Simplified cache fsm. --- pipelined/src/cache/cachefsm.sv | 37 +++++++++++++++++---------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 0fd7f5d5..1daa5a89 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -80,11 +80,11 @@ module cachefsm logic [1:0] PreSelAdr; logic resetDelay; - logic Read, Write, AMO; + logic AMO; logic DoAMO, DoRead, DoWrite, DoFlush; - logic DoAMOHit, DoReadHit, DoWriteHit; - logic DoAMOMiss, DoReadMiss, DoWriteMiss; - logic FlushFlag; + logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyHit; + logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss; + logic FlushFlag, FlushWayAndNotAdrFlag; typedef enum logic [3:0] {STATE_READY, @@ -118,15 +118,15 @@ module cachefsm assign DoAMO = AMO & ~IgnoreRequest; assign DoAMOHit = DoAMO & CacheHit; assign DoAMOMiss = DoAMO & ~CacheHit; - assign Read = RW[1]; - assign DoRead = Read & ~IgnoreRequest; + assign DoRead = RW[1] & ~IgnoreRequest; assign DoReadHit = DoRead & CacheHit; assign DoReadMiss = DoRead & ~CacheHit; - assign Write = RW[0]; - assign DoWrite = Write & ~IgnoreRequest; + assign DoWrite = RW[0] & ~IgnoreRequest; assign DoWriteHit = DoWrite & CacheHit; assign DoWriteMiss = DoWrite & ~CacheHit; + assign DoAnyMiss = DoAMOMiss | DoReadMiss | DoWriteMiss; + assign DoAnyHit = DoAMOHit | DoReadHit | DoWriteHit; assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. @@ -158,7 +158,7 @@ module cachefsm STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_MISS_WRITE_CACHE_LINE; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; - STATE_MISS_READ_WORD: if (Write & ~AMO) NextState = STATE_MISS_WRITE_WORD; + STATE_MISS_READ_WORD: if (RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; else NextState = STATE_MISS_READ_WORD_DELAY; STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; else if(CPUBusy) NextState = STATE_CPU_BUSY; @@ -188,7 +188,7 @@ module cachefsm // com back to CPU assign CacheCommitted = CurrState != STATE_READY; - assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) | + assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | @@ -212,7 +212,7 @@ module cachefsm (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_WRITE_WORD); assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE); - assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) | + assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | (CurrState == STATE_MISS_READ_WORD_DELAY) | (CurrState == STATE_MISS_WRITE_WORD); // Flush and eviction controls @@ -220,27 +220,28 @@ module cachefsm assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayFlag & ~FlushAdrFlag) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag); + assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; + assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag); assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls - assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss)); + assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss); assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); // handle cpu stall. assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY; - assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | Read) & CPUBusy) | + assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) | (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; // **** can this be simplified? assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. (CurrState == STATE_READY & (AMO & CacheHit)) | - (CurrState == STATE_READY & (Read & CacheHit) & (CPUBusy & `REPLAY)) | - (CurrState == STATE_READY & (Write & CacheHit)) | + (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | + (CurrState == STATE_READY & (RW[0] & CacheHit)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | From e2e0a4f5959fe2185e4799b4bff3ae5aac9b1f7b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 15:09:00 -0600 Subject: [PATCH 02/12] Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. --- pipelined/src/cache/cachefsm.sv | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 1daa5a89..8354b765 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -97,7 +97,6 @@ module cachefsm STATE_MISS_WRITE_WORD, STATE_CPU_BUSY, - STATE_CPU_BUSY_FINISH_AMO, STATE_FLUSH, STATE_FLUSH_CHECK, @@ -148,7 +147,7 @@ module cachefsm case (CurrState) STATE_READY: if(IgnoreRequest) NextState = STATE_READY; else if(DoFlush) NextState = STATE_FLUSH; - else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; // change + else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY; // change else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY; else if(DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY; else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; // change @@ -160,7 +159,7 @@ module cachefsm STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; STATE_MISS_READ_WORD: if (RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; else NextState = STATE_MISS_READ_WORD_DELAY; - STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; + STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY; else if(CPUBusy) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; @@ -169,8 +168,6 @@ module cachefsm else NextState = STATE_MISS_EVICT_DIRTY; STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; - STATE_CPU_BUSY_FINISH_AMO: if(CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; - else NextState = STATE_READY; STATE_FLUSH: NextState = STATE_FLUSH_CHECK; STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; else if (FlushFlag) NextState = STATE_READY; @@ -232,7 +229,7 @@ module cachefsm assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); // handle cpu stall. - assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY; + assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY; assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) | (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) | (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; @@ -249,8 +246,7 @@ module cachefsm (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | (CurrState == STATE_MISS_WRITE_WORD) | (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | - (CurrState == STATE_CPU_BUSY_FINISH_AMO)) ? 2'b01 : + (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY))) ? 2'b01 : ((CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) | (CurrState == STATE_FLUSH_INCR) | From 52894a7a4f39f4fb6d7cccdc1ab19308a540b330 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 15:16:45 -0600 Subject: [PATCH 03/12] Cache fsm simplifications. --- pipelined/src/cache/cachefsm.sv | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 8354b765..c80d52db 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -82,7 +82,7 @@ module cachefsm logic resetDelay; logic AMO; logic DoAMO, DoRead, DoWrite, DoFlush; - logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyHit; + logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyUpdateHit, DoAnyHit; logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss; logic FlushFlag, FlushWayAndNotAdrFlag; @@ -124,8 +124,9 @@ module cachefsm assign DoWriteHit = DoWrite & CacheHit; assign DoWriteMiss = DoWrite & ~CacheHit; - assign DoAnyMiss = DoAMOMiss | DoReadMiss | DoWriteMiss; - assign DoAnyHit = DoAMOHit | DoReadHit | DoWriteHit; + assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; + assign DoAnyUpdateHit = DoAMOHit | DoWriteHit; + assign DoAnyHit = DoAnyUpdateHit | DoReadHit; assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. @@ -147,10 +148,8 @@ module cachefsm case (CurrState) STATE_READY: if(IgnoreRequest) NextState = STATE_READY; else if(DoFlush) NextState = STATE_FLUSH; - else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY; // change - else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY; - else if(DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY; - else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; // change + else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY; + else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change else NextState = STATE_READY; STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE; else NextState = STATE_MISS_FETCH_WDV; @@ -205,7 +204,7 @@ module cachefsm (CurrState == STATE_MISS_WRITE_WORD); assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) | + assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAnyUpdateHit)) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_WRITE_WORD); assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE); From 1255e82154ee1ef7997cab574a2d4f12d291224d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 22:23:47 -0600 Subject: [PATCH 04/12] Removed redundant signals from cache. --- pipelined/src/cache/cache.sv | 8 +-- pipelined/src/cache/cachefsm.sv | 109 ++++++++++++++------------------ 2 files changed, 53 insertions(+), 64 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index a4f73e8f..4e4dd67e 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -175,9 +175,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // *** change to structural mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay); - assign SetValidWay = SetValid ? SelectedWay : '0; + assign SetValidWay = FSMLineWriteEn ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; - assign SetDirtyWay = SetDirty ? SelectedWay : '0; + assign SetDirtyWay = FSMWordWriteEn ? SelectedWay : '0; assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0; assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0; @@ -190,8 +190,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdr, .SetValid, - .ClearValid, .SetDirty, .ClearDirty, .FSMWordWriteEn, + .CacheMiss, .CacheAccess, .SelAdr, + .ClearValid, .ClearDirty, .FSMWordWriteEn, .FSMLineWriteEn, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index c80d52db..c0e4a29d 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -62,9 +62,7 @@ module cachefsm // dcache internals output logic [1:0] SelAdr, - output logic SetValid, output logic ClearValid, - output logic SetDirty, output logic ClearDirty, output logic FSMWordWriteEn, output logic FSMLineWriteEn, @@ -78,12 +76,11 @@ module cachefsm output logic save, output logic restore); - logic [1:0] PreSelAdr; logic resetDelay; logic AMO; logic DoAMO, DoRead, DoWrite, DoFlush; - logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyUpdateHit, DoAnyHit; - logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss; + logic DoAnyUpdateHit, DoAnyHit; + logic DoAnyMiss; logic FlushFlag, FlushWayAndNotAdrFlag; typedef enum logic [3:0] {STATE_READY, @@ -111,22 +108,15 @@ module cachefsm // if the command is used in the READY state then the cache needs to be able to supress // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. - // need to re organize all of these. Low priority though. assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. assign AMO = Atomic[1] & (&RW); assign DoAMO = AMO & ~IgnoreRequest; - assign DoAMOHit = DoAMO & CacheHit; - assign DoAMOMiss = DoAMO & ~CacheHit; assign DoRead = RW[1] & ~IgnoreRequest; - assign DoReadHit = DoRead & CacheHit; - assign DoReadMiss = DoRead & ~CacheHit; assign DoWrite = RW[0] & ~IgnoreRequest; - assign DoWriteHit = DoWrite & CacheHit; - assign DoWriteMiss = DoWrite & ~CacheHit; assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; - assign DoAnyUpdateHit = DoAMOHit | DoWriteHit; - assign DoAnyHit = DoAnyUpdateHit | DoReadHit; + assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; + assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit); assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. @@ -137,7 +127,6 @@ module cachefsm // PCNextF will no longer be pointing to the correct address. // But PCF will be the reset vector. flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); - assign SelAdr = resetDelay ? 2'b01 : PreSelAdr; always_ff @(posedge clk) if (reset) CurrState <= #1 STATE_READY; @@ -146,39 +135,39 @@ module cachefsm always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(IgnoreRequest) NextState = STATE_READY; - else if(DoFlush) NextState = STATE_FLUSH; - else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY; - else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change - else NextState = STATE_READY; - STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE; - else NextState = STATE_MISS_FETCH_WDV; - STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; - else NextState = STATE_MISS_WRITE_CACHE_LINE; - STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; - STATE_MISS_READ_WORD: if (RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; - else NextState = STATE_MISS_READ_WORD_DELAY; - STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY; - else if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; - else NextState = STATE_MISS_EVICT_DIRTY; - STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_FLUSH: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; - else if (FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; - else NextState = STATE_FLUSH_WRITE_BACK; - STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY; - else if (FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - default: NextState = STATE_READY; + STATE_READY: if(IgnoreRequest) NextState = STATE_READY; + else if(DoFlush) NextState = STATE_FLUSH; + else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY; + else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change + else NextState = STATE_READY; + STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_FETCH_DONE; + else NextState = STATE_MISS_FETCH_WDV; + STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + else NextState = STATE_MISS_WRITE_CACHE_LINE; + STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; + STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; + else NextState = STATE_MISS_READ_WORD_DELAY; + STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY; + else if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; + else NextState = STATE_MISS_EVICT_DIRTY; + STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_FLUSH: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; + else if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; + else NextState = STATE_FLUSH_WRITE_BACK; + STATE_FLUSH_CLEAR_DIRTY: if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + default: NextState = STATE_READY; endcase end @@ -196,21 +185,19 @@ module cachefsm (CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); // write enables internal to cache - assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; + assign FSMLineWriteEn = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign ClearValid = '0; - assign SetDirty = (CurrState == STATE_READY & DoAMO) | - (CurrState == STATE_READY & DoWrite) | - (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | - (CurrState == STATE_MISS_WRITE_WORD); - assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAnyUpdateHit)) | + assign FSMWordWriteEn = (CurrState == STATE_READY & DoAnyUpdateHit) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_WRITE_WORD); - assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE); + + assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY); + assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | (CurrState == STATE_MISS_READ_WORD_DELAY) | (CurrState == STATE_MISS_WRITE_WORD); + // Flush and eviction controls assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | @@ -220,7 +207,7 @@ module cachefsm assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) | (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag); assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); + (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~FlushFlag); assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls @@ -234,7 +221,8 @@ module cachefsm (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; // **** can this be simplified? - assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. + assign SelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. + // use the raw requests as we don't want IgnoreRequestTrapM in the critical path (CurrState == STATE_READY & (AMO & CacheHit)) | (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_READY & (RW[0] & CacheHit)) | @@ -245,7 +233,8 @@ module cachefsm (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | (CurrState == STATE_MISS_WRITE_WORD) | (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY))) ? 2'b01 : + (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | + resetDelay) ? 2'b01 : ((CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) | (CurrState == STATE_FLUSH_INCR) | From b11e9eca7b5c6364e51d0c818d03c90ef1582134 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 22:27:27 -0600 Subject: [PATCH 05/12] Reduced complexity of the address selection during flush. --- pipelined/src/cache/cache.sv | 4 ++-- pipelined/src/cache/cachefsm.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 4e4dd67e..bf34a680 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -71,8 +71,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [1:0] SelAdr; logic [SETLEN-1:0] RAdr; logic [LINELEN-1:0] CacheWriteData; - logic SetValid, ClearValid; - logic SetDirty, ClearDirty; + logic ClearValid; + logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index c0e4a29d..3b9201fa 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -236,10 +236,10 @@ module cachefsm (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | resetDelay) ? 2'b01 : ((CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) | + (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 : + (CurrState == STATE_FLUSH_CLEAR_DIRTY)) ? 2'b10 : 2'b00; From 16abe90a0d93e4c301e2139fa9b0b2a2eb29c06d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 22:41:36 -0600 Subject: [PATCH 06/12] Reduced seladr to 1 bit as second bit is same as selflush. --- pipelined/src/cache/cache.sv | 4 +- pipelined/src/cache/cachefsm.sv | 105 +++++++++++++++----------------- 2 files changed, 50 insertions(+), 59 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index bf34a680..b9e6ae2a 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -68,7 +68,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( localparam WORDSPERLINE = LINELEN/`XLEN; localparam FlushAdrThreshold = NUMLINES - 1; - logic [1:0] SelAdr; + logic SelAdr; logic [SETLEN-1:0] RAdr; logic [LINELEN-1:0] CacheWriteData; logic ClearValid; @@ -110,7 +110,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // and FlushAdr when handling D$ flushes mux3 #(SETLEN) AdrSelMux( .d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr), - .s(SelAdr), .y(RAdr)); + .s({SelFlush, SelAdr}), .y(RAdr)); // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 3b9201fa..3586965a 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -32,49 +32,49 @@ module cachefsm (input logic clk, - input logic reset, + input logic reset, // inputs from IEU - input logic [1:0] RW, - input logic [1:0] Atomic, - input logic FlushCache, + input logic [1:0] RW, + input logic [1:0] Atomic, + input logic FlushCache, // hazard inputs - input logic CPUBusy, + input logic CPUBusy, // interlock fsm - input logic IgnoreRequestTLB, - input logic IgnoreRequestTrapM, + input logic IgnoreRequestTLB, + input logic IgnoreRequestTrapM, // Bus inputs - input logic CacheBusAck, + input logic CacheBusAck, // dcache internals - input logic CacheHit, - input logic VictimDirty, - input logic FlushAdrFlag, - input logic FlushWayFlag, + input logic CacheHit, + input logic VictimDirty, + input logic FlushAdrFlag, + input logic FlushWayFlag, // hazard outputs - output logic CacheStall, + output logic CacheStall, // counter outputs - output logic CacheMiss, - output logic CacheAccess, + output logic CacheMiss, + output logic CacheAccess, // Bus outputs - output logic CacheCommitted, - output logic CacheWriteLine, - output logic CacheFetchLine, + output logic CacheCommitted, + output logic CacheWriteLine, + output logic CacheFetchLine, // dcache internals - output logic [1:0] SelAdr, - output logic ClearValid, - output logic ClearDirty, - output logic FSMWordWriteEn, - output logic FSMLineWriteEn, - output logic SelEvict, - output logic LRUWriteEn, - output logic SelFlush, - output logic FlushAdrCntEn, - output logic FlushWayCntEn, - output logic FlushAdrCntRst, - output logic FlushWayCntRst, - output logic save, - output logic restore); + output logic SelAdr, + output logic ClearValid, + output logic ClearDirty, + output logic FSMWordWriteEn, + output logic FSMLineWriteEn, + output logic SelEvict, + output logic LRUWriteEn, + output logic SelFlush, + output logic FlushAdrCntEn, + output logic FlushWayCntEn, + output logic FlushAdrCntRst, + output logic FlushWayCntRst, + output logic save, + output logic restore); logic resetDelay; logic AMO; @@ -186,18 +186,15 @@ module cachefsm (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); // write enables internal to cache assign FSMLineWriteEn = CurrState == STATE_MISS_WRITE_CACHE_LINE; - assign ClearValid = '0; assign FSMWordWriteEn = (CurrState == STATE_READY & DoAnyUpdateHit) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_WRITE_WORD); - + assign ClearValid = '0; assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | (CurrState == STATE_MISS_READ_WORD_DELAY) | (CurrState == STATE_MISS_WRITE_WORD); - // Flush and eviction controls assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | @@ -221,26 +218,20 @@ module cachefsm (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; // **** can this be simplified? - assign SelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. - // use the raw requests as we don't want IgnoreRequestTrapM in the critical path - (CurrState == STATE_READY & (AMO & CacheHit)) | - (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | - (CurrState == STATE_READY & (RW[0] & CacheHit)) | - (CurrState == STATE_MISS_FETCH_WDV) | - (CurrState == STATE_MISS_FETCH_DONE) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_MISS_READ_WORD) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | - (CurrState == STATE_MISS_WRITE_WORD) | - (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | - resetDelay) ? 2'b01 : - ((CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_CHECK) | - (CurrState == STATE_FLUSH_INCR) | - (CurrState == STATE_FLUSH_WRITE_BACK) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY)) ? 2'b10 : - 2'b00; - + assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. + // use the raw requests as we don't want IgnoreRequestTrapM in the critical path + (CurrState == STATE_READY & ((AMO | RW[0]) & CacheHit)) | // changes if store delay hazard removed + (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | + + (CurrState == STATE_MISS_FETCH_WDV) | + (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_EVICT_DIRTY) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_MISS_READ_WORD) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | + (CurrState == STATE_MISS_WRITE_WORD) | + + (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | + resetDelay; endmodule // cachefsm From bf173b035c4683b441838d469a7780abb35e0066 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 22:54:05 -0600 Subject: [PATCH 07/12] More cache simplifications. --- pipelined/src/cache/cachefsm.sv | 36 ++++++++++++++++----------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 3586965a..388908c2 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -83,23 +83,23 @@ module cachefsm logic DoAnyMiss; logic FlushFlag, FlushWayAndNotAdrFlag; - typedef enum logic [3:0] {STATE_READY, - - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_EVICT_DIRTY, - STATE_MISS_WRITE_CACHE_LINE, - STATE_MISS_READ_WORD, - STATE_MISS_READ_WORD_DELAY, - STATE_MISS_WRITE_WORD, - - STATE_CPU_BUSY, - - STATE_FLUSH, - STATE_FLUSH_CHECK, - STATE_FLUSH_INCR, - STATE_FLUSH_WRITE_BACK, - STATE_FLUSH_CLEAR_DIRTY} statetype; + typedef enum logic [3:0] {STATE_READY, // hit states + // miss states + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_EVICT_DIRTY, + STATE_MISS_WRITE_CACHE_LINE, + STATE_MISS_READ_WORD, + STATE_MISS_READ_WORD_DELAY, + STATE_MISS_WRITE_WORD, + // cpu stalled replay/restore state + STATE_CPU_BUSY, + // flush cache + STATE_FLUSH, + STATE_FLUSH_CHECK, + STATE_FLUSH_INCR, + STATE_FLUSH_WRITE_BACK, + STATE_FLUSH_CLEAR_DIRTY} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; logic IgnoreRequest; @@ -176,9 +176,9 @@ module cachefsm assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_MISS_READ_WORD) | - (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) | (CurrState == STATE_FLUSH_INCR) | From dd944265aa07b72f28089569066885298954a86c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 23:10:58 -0600 Subject: [PATCH 08/12] Formating improvements to cache. --- pipelined/src/cache/cache.sv | 27 ++++++++++--------------- pipelined/src/cache/cachefsm.sv | 4 ++-- pipelined/src/cache/cacheway.sv | 35 +++++++++++++++------------------ 3 files changed, 28 insertions(+), 38 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index b9e6ae2a..761fe5ae 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -74,7 +74,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] WayHit; + logic [NUMWAYS-1:0] WayHit, WayHitSaved, WayHitFinal; logic CacheHit; logic FSMWordWriteEn; logic FSMLineWriteEn; @@ -97,7 +97,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic LRUWriteEn; logic SelFlush; logic ResetOrFlushAdr, ResetOrFlushWay; - logic [NUMWAYS-1:0] WayHitSaved, WayHitFinal; logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn; @@ -110,7 +109,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // and FlushAdr when handling D$ flushes mux3 #(SETLEN) AdrSelMux( .d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr), - .s({SelFlush, SelAdr}), .y(RAdr)); + .s({SelFlush, SelAdr}), .y(RAdr)); // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( @@ -130,7 +129,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); - // Because of the sram clocked read when the ieu is stalled the read data maybe lost. // There are two ways to resolve. 1. We can replay the read of the sram or we can save // the data. Replay is eaiser but creates a longer critical path. @@ -143,38 +141,34 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(CacheWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), - .s({SelFlush, SelEvict}), - .y(CacheBusAdr)); + .s({SelFlush, SelEvict}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Flush address and way generation during flush ///////////////////////////////////////////////////////////////////////////////////////////// - + // *** this could be improved. reduce to a single adder of size $clog2(numway+numlines) assign ResetOrFlushAdr = reset | FlushAdrCntRst; - flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), - .en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr)); + flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn), + .d(FlushAdrP1), .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); assign ResetOrFlushWay = reset | FlushWayCntRst; - flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), - .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), - .d(NextFlushWay), .q(FlushWay)); + flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), + .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// - - // *** change to structural - mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay); + mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, + {SelFlush, FSMLineWriteEn}, SelectedWay); assign SetValidWay = FSMLineWriteEn ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; assign SetDirtyWay = FSMWordWriteEn ? SelectedWay : '0; @@ -186,7 +180,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 388908c2..820738ca 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -224,9 +224,9 @@ module cachefsm (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_MISS_FETCH_WDV) | - (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_MISS_READ_WORD) | (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | (CurrState == STATE_MISS_WRITE_WORD) | diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index a5bb5281..c3429eeb 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -59,21 +59,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGXLENBYTES = $clog2(`XLEN/8); - logic [NUMLINES-1:0] ValidBits; - logic [NUMLINES-1:0] DirtyBits; - logic [LINELEN-1:0] ReadDataLine; - logic [TAGLEN-1:0] ReadTag; - logic Valid; - logic Dirty; - logic SelData; - logic SelTag; - - logic [$clog2(NUMLINES)-1:0] RAdrD; - - logic [2**LOGWPL-1:0] MemPAdrDecoded; - logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; + logic [NUMLINES-1:0] ValidBits; + logic [NUMLINES-1:0] DirtyBits; + logic [LINELEN-1:0] ReadDataLine; + logic [TAGLEN-1:0] ReadTag; + logic Valid; + logic Dirty; + logic SelData; + logic SelTag; + logic [$clog2(NUMLINES)-1:0] RAdrD; + logic [2**LOGWPL-1:0] MemPAdrDecoded; + logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// @@ -118,9 +115,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset | InvalidateAll) ValidBits <= #1 '0; - else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; - else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; + if (reset | InvalidateAll) ValidBits <= #1 '0; + else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; + else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; end flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); assign Valid = ValidBits[RAdrD]; @@ -132,8 +129,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // Dirty bits if (DIRTY_BITS) begin:dirty always_ff @(posedge clk) begin - if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; - else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; + if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; + else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0; end assign Dirty = DirtyBits[RAdrD]; From a5ad4331ecc96254e6c4fa7111a2fb3b9e3a2743 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Feb 2022 12:38:39 -0600 Subject: [PATCH 09/12] More cache cleanup. --- pipelined/src/cache/cache.sv | 2 -- pipelined/src/cache/cachefsm.sv | 3 +-- pipelined/src/cache/cacheway.sv | 4 ++-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 761fe5ae..bf248e6a 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -151,13 +151,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Flush address and way generation during flush ///////////////////////////////////////////////////////////////////////////////////////////// - // *** this could be improved. reduce to a single adder of size $clog2(numway+numlines) assign ResetOrFlushAdr = reset | FlushAdrCntRst; flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); - assign ResetOrFlushWay = reset | FlushWayCntRst; flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 820738ca..5cd564b6 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -147,8 +147,7 @@ module cachefsm STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; else NextState = STATE_MISS_READ_WORD_DELAY; - STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY; - else if(CPUBusy) NextState = STATE_CPU_BUSY; + STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index c3429eeb..86ccf426 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -88,9 +88,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn)); // AND portion of distributed tag multiplexer - assign SelTag = SelFlush ? FlushWay : VictimWay; + mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign VictimDirtyWay = SelTag & Dirty & Valid; + assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); ///////////////////////////////////////////////////////////////////////////////////////////// // Data Array @@ -106,7 +107,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, end // AND portion of distributed read multiplexers - assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData); assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux. From 7ffbc6b2abc23e10a4659cbcf7a181c178bda5b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Feb 2022 15:06:18 -0600 Subject: [PATCH 10/12] Changed names of signals in cache. --- pipelined/regression/fpga-wave.do | 4 +- pipelined/regression/linux-wave.do | 10 +- pipelined/regression/wave-coremark.do | 4 +- pipelined/regression/wave.do | 455 +++++++++++++------------- pipelined/src/cache/cache.sv | 22 +- pipelined/src/cache/cachefsm.sv | 8 +- pipelined/src/ifu/ifu.sv | 6 +- pipelined/src/lsu/busdp.sv | 6 +- pipelined/src/lsu/lsu.sv | 6 +- 9 files changed, 260 insertions(+), 261 deletions(-) diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index 53c80c17..ecda3c25 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -251,7 +251,7 @@ add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipel add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/InstrReadF add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/InstrAckF add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/ICacheMemWriteEnable -add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/ICacheMemWriteData +add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/ICacheBusWriteData add wave -noupdate -group AHB -color Gold /testbench/dut/wallypipelinedsoc/core/ebu/BusState add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/core/ebu/AtomicMaskedM @@ -285,7 +285,7 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipeline add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SelAdrM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheMemWriteData +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheBusWriteData add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushWay add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirty add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VDWriteEnableWay diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index cf9ac014..b039dbe4 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -188,7 +188,7 @@ add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheMemWriteData +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress @@ -212,8 +212,8 @@ add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FSMLineWriteEn -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FSMWordWriteEn +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE @@ -227,7 +227,7 @@ add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/ add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} @@ -331,7 +331,7 @@ add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/ls add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine -add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr diff --git a/pipelined/regression/wave-coremark.do b/pipelined/regression/wave-coremark.do index cf883723..2d54a8e5 100644 --- a/pipelined/regression/wave-coremark.do +++ b/pipelined/regression/wave-coremark.do @@ -211,7 +211,7 @@ add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/b add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/InstrReadF add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/InstrAckF add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/ICacheMemWriteEnable -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/ICacheMemWriteData +add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/ICacheBusWriteData add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM @@ -244,7 +244,7 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus. add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SelAdrM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/ReadDataBlockM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheMemWriteData +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheBusWriteData add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WriteEnable} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetValid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetDirty} diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 52eb8938..5fa34a4d 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -175,195 +175,186 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED -add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr -add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FSMLineWriteEn -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FSMWordWriteEn -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty - -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} - - -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} - -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} - -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} - - -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr +add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR @@ -443,48 +434,56 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/MEPC_REGW add wave -noupdate /testbench/dut/core/lsu/bus/busdp/LocalLSUBusAdr add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheFetchLine add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheWriteLine -add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAdr -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusHRDATA -add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF -add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState -add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 -add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF -add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheMemWriteData -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA +add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF +add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState +add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 +add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF +add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress add wave -noupdate /testbench/dut/core/ifu/IFUBusRead add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/CacheFetchLine add wave -noupdate -radix unsigned -childformat {{{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[31]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[30]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[29]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[28]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[27]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[26]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[25]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[1]} -radix unsigned} {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -radix unsigned}} -subitemconfig {{/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[31]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[30]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[29]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[28]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[27]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[26]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[25]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[1]} {-height 16 -radix unsigned} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} {-height 16 -radix unsigned}} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW -add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrAllThreshold +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrAll +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrAllP1 +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrAllFlag +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushSetAdrAll +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayEncAll +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayAll TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {6451242 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} +WaveRestoreCursors {{Cursor 7} {34475 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -500,4 +499,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {593782 ns} {7438712 ns} +WaveRestoreZoom {34303 ns} {34653 ns} diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index bf248e6a..1404e61d 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -56,7 +56,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( output logic CacheWriteLine, input logic CacheBusAck, output logic [`PA_BITS-1:0] CacheBusAdr, - input logic [LINELEN-1:0] CacheMemWriteData, + input logic [LINELEN-1:0] CacheBusWriteData, output logic [LINELEN-1:0] ReadDataLine); // Cache parameters @@ -76,8 +76,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit, WayHitSaved, WayHitFinal; logic CacheHit; - logic FSMWordWriteEn; - logic FSMLineWriteEn; + logic SetDirty; + logic SetValid; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; logic VictimDirty; @@ -142,7 +142,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(CacheWriteData)); + .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), @@ -166,13 +166,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, - {SelFlush, FSMLineWriteEn}, SelectedWay); - assign SetValidWay = FSMLineWriteEn ? SelectedWay : '0; + {SelFlush, SetValid}, SelectedWay); + assign SetValidWay = SetValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; - assign SetDirtyWay = FSMWordWriteEn ? SelectedWay : '0; + assign SetDirtyWay = SetDirty ? SelectedWay : '0; assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; - assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0; - assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0; + assign WriteWordWayEn = SetDirty ? SelectedWay : '0; + assign WriteLineWayEn = SetValid ? SelectedWay : '0; ///////////////////////////////////////////////////////////////////////////////////////////// @@ -182,8 +182,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, - .ClearValid, .ClearDirty, .FSMWordWriteEn, - .FSMLineWriteEn, .SelEvict, .SelFlush, + .ClearValid, .ClearDirty, .SetDirty, + .SetValid, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .save, .restore, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 5cd564b6..df05e6cb 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -64,8 +64,8 @@ module cachefsm output logic SelAdr, output logic ClearValid, output logic ClearDirty, - output logic FSMWordWriteEn, - output logic FSMLineWriteEn, + output logic SetDirty, + output logic SetValid, output logic SelEvict, output logic LRUWriteEn, output logic SelFlush, @@ -184,8 +184,8 @@ module cachefsm (CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); // write enables internal to cache - assign FSMLineWriteEn = CurrState == STATE_MISS_WRITE_CACHE_LINE; - assign FSMWordWriteEn = (CurrState == STATE_READY & DoAnyUpdateHit) | + assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; + assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_WRITE_WORD); assign ClearValid = '0; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 62f93ab5..9d2f6561 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -184,7 +184,7 @@ module ifu ( localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] ReadDataLine; - logic [LINELEN-1:0] ICacheMemWriteData; + logic [LINELEN-1:0] ICacheBusWriteData; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; logic save,restore; @@ -198,7 +198,7 @@ module ifu ( .WordCount(), .LSUBusHWDATA(), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), - .DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF), + .DCacheBusWriteData(ICacheBusWriteData), .LSUPAdrM(PCPF), .FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]), .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); @@ -211,7 +211,7 @@ module ifu ( .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0), - .CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck), + .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(), .ReadDataLine(ReadDataLine), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 79545254..54bfa4e4 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -52,7 +52,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0) input logic DCacheFetchLine, input logic DCacheWriteLine, output logic DCacheBusAck, - output logic [LINELEN-1:0] DCacheMemWriteData, + output logic [LINELEN-1:0] DCacheBusWriteData, // lsu interface input logic [`PA_BITS-1:0] LSUPAdrM, @@ -77,7 +77,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0) for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), - .d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); + .d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); end @@ -88,7 +88,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0) else assign LSUBusHWDATA = '0; mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); - mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[WORDLEN-1:0]), + mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[WORDLEN-1:0]), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix. diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f6c8ec47..60f35ec4 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -185,7 +185,7 @@ module lsu ( localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] ReadDataLineM; - logic [LINELEN-1:0] DCacheMemWriteData; + logic [LINELEN-1:0] DCacheBusWriteData; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; @@ -200,7 +200,7 @@ module lsu ( .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, - .DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM, + .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .FinalAMOWriteDataM, .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); @@ -218,7 +218,7 @@ module lsu ( .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM), - .CacheMemWriteData(DCacheMemWriteData), .CacheFetchLine(DCacheFetchLine), + .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( From 1d7949513ddb24254025138ef70096be398a52bf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Feb 2022 15:47:27 -0600 Subject: [PATCH 11/12] More cache cleanup. --- pipelined/regression/fpga-wave.do | 14 +++--- pipelined/regression/linux-wave.do | 16 +++---- pipelined/regression/wave-coremark.do | 14 +++--- pipelined/regression/wave.do | 16 +++---- pipelined/src/cache/cache.sv | 18 ++++---- pipelined/src/cache/cachereplacementpolicy.sv | 44 +++++++++---------- pipelined/src/cache/cacheway.sv | 13 +++--- 7 files changed, 68 insertions(+), 67 deletions(-) diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index ecda3c25..e95321f5 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -174,7 +174,7 @@ add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/MulDi add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/DivBusyE add wave -noupdate -group icache -color Gold /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/CurrState add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/BasePAdrF -add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/WayHit +add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/HitWay add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/BlockReplacementBits add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/EncVicWay add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/VictimWay @@ -349,23 +349,23 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} - add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearValid add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetDirty add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HitWay add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockWayMaskedM add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordM add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordMuxM @@ -385,7 +385,7 @@ add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /t add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataM add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheStallM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HitWay add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheHit add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCount add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCountFlag diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index b039dbe4..e980372c 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -183,7 +183,7 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLB add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr @@ -211,7 +211,7 @@ add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr @@ -298,23 +298,23 @@ add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} - add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay @@ -327,7 +327,7 @@ add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine diff --git a/pipelined/regression/wave-coremark.do b/pipelined/regression/wave-coremark.do index 2d54a8e5..20248f35 100644 --- a/pipelined/regression/wave-coremark.do +++ b/pipelined/regression/wave-coremark.do @@ -176,7 +176,7 @@ add wave -noupdate -group muldiv /testbench/dut/core/mdu/MulDivResultW add wave -noupdate -group muldiv /testbench/dut/core/mdu/DivBusyE add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/bus/icache/controller/CurrState add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/BasePAdrF -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/WayHit +add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/HitWay add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/VictimWay add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/WriteEnable} add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/SetValid} @@ -304,23 +304,23 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} - add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearValid add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetDirty add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/HitWay} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Valid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Dirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/HitWay add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataBlockWayMaskedM add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordM add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordMuxM @@ -340,7 +340,7 @@ add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/ReadDataM add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/DCacheStallM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/HitWay add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/CacheHit add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/FetchCount add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/FetchCountFlag diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 5fa34a4d..98869adc 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -192,7 +192,7 @@ add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusA add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr @@ -277,23 +277,23 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay @@ -306,7 +306,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine @@ -448,7 +448,7 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLB add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 1404e61d..a0e719b6 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -74,7 +74,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] WayHit, WayHitSaved, WayHitFinal; + logic [NUMWAYS-1:0] HitWay, HitWaySaved, HitWayFinal; logic CacheHit; logic SetDirty; logic SetValid; @@ -115,13 +115,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( .clk, .reset, .RAdr, .PAdr, .WriteWordWayEn, .WriteLineWayEn, .CacheWriteData, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, - .FlushWay, .SelFlush, .ReadDataLineWay, .WayHit, .VictimDirtyWay, .VictimTagWay, - .InvalidateAll(InvalidateCacheM)); + .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, + .Invalidate(InvalidateCacheM)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .WayHit(WayHitFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn); + .clk, .reset, .HitWay(HitWayFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. - assign CacheHit = | WayHit; + assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; // ReadDataLineWay is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. @@ -134,9 +134,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // the data. Replay is eaiser but creates a longer critical path. // save/restore only wayhit and readdata. if(!`REPLAY) begin - flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHit, WayHitSaved); - mux2 #(NUMWAYS) saverestoremux(WayHit, WayHitSaved, restore, WayHitFinal); - end else assign WayHitFinal = WayHit; + flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved); + mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); + end else assign HitWayFinal = HitWay; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. @@ -165,7 +165,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// - mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, + mux3 #(NUMWAYS) selectwaymux(HitWayFinal, VictimWay, FlushWay, {SelFlush, SetValid}, SelectedWay); assign SetValidWay = SetValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 49f0f79c..818a0abe 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -32,7 +32,7 @@ module cachereplacementpolicy #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( input logic clk, reset, - input logic [NUMWAYS-1:0] WayHit, + input logic [NUMWAYS-1:0] HitWay, output logic [NUMWAYS-1:0] VictimWay, input logic [`PA_BITS-1:0] PAdr, input logic [SETLEN-1:0] RAdr, @@ -67,7 +67,7 @@ module cachereplacementpolicy genvar index; if(NUMWAYS == 2) begin : PseudoLRU assign LRUEn[0] = 1'b0; - assign NewReplacement[0] = WayHit[1]; + assign NewReplacement[0] = HitWay[1]; assign VictimWay[1] = ~LineReplacementBits[0]; assign VictimWay[0] = LineReplacementBits[0]; end else if (NUMWAYS == 4) begin : PseudoLRU @@ -84,15 +84,15 @@ module cachereplacementpolicy assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1]; assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1]; - // New LRU bits which are updated is function only of the WayHit. + // New LRU bits which are updated is function only of the HitWay. // However the not updated bits come from the old LRU. - assign LRUEn[2] = |WayHit; - assign LRUEn[1] = WayHit[3] | WayHit[2]; - assign LRUEn[0] = WayHit[1] | WayHit[0]; + assign LRUEn[2] = |HitWay; + assign LRUEn[1] = HitWay[3] | HitWay[2]; + assign LRUEn[0] = HitWay[1] | HitWay[0]; - assign LRUMask[2] = WayHit[1] | WayHit[0]; - assign LRUMask[1] = WayHit[2]; - assign LRUMask[0] = WayHit[0]; + assign LRUMask[2] = HitWay[1] | HitWay[0]; + assign LRUMask[1] = HitWay[2]; + assign LRUMask[0] = HitWay[0]; mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement); end @@ -101,21 +101,21 @@ module cachereplacementpolicy // selects assign LRUEn[6] = 1'b1; - assign LRUEn[5] = WayHit[7] | WayHit[6] | WayHit[5] | WayHit[4]; - assign LRUEn[4] = WayHit[7] | WayHit[6]; - assign LRUEn[3] = WayHit[5] | WayHit[4]; - assign LRUEn[2] = WayHit[3] | WayHit[2] | WayHit[1] | WayHit[0]; - assign LRUEn[1] = WayHit[3] | WayHit[2]; - assign LRUEn[0] = WayHit[1] | WayHit[0]; + assign LRUEn[5] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4]; + assign LRUEn[4] = HitWay[7] | HitWay[6]; + assign LRUEn[3] = HitWay[5] | HitWay[4]; + assign LRUEn[2] = HitWay[3] | HitWay[2] | HitWay[1] | HitWay[0]; + assign LRUEn[1] = HitWay[3] | HitWay[2]; + assign LRUEn[0] = HitWay[1] | HitWay[0]; // mask - assign LRUMask[6] = WayHit[7] | WayHit[6] | WayHit[5] | WayHit[4]; - assign LRUMask[5] = WayHit[7] | WayHit[6]; - assign LRUMask[4] = WayHit[7]; - assign LRUMask[3] = WayHit[5]; - assign LRUMask[2] = WayHit[3] | WayHit[2]; - assign LRUMask[1] = WayHit[2]; - assign LRUMask[0] = WayHit[0]; + assign LRUMask[6] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4]; + assign LRUMask[5] = HitWay[7] | HitWay[6]; + assign LRUMask[4] = HitWay[7]; + assign LRUMask[3] = HitWay[5]; + assign LRUMask[2] = HitWay[3] | HitWay[2]; + assign LRUMask[1] = HitWay[2]; + assign LRUMask[0] = HitWay[0]; for(index = 0; index < NUMWAYS-1; index++) assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 86ccf426..2855f3fa 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -45,13 +45,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic SetDirtyWay, input logic ClearDirtyWay, input logic SelEvict, - input logic VictimWay, - input logic InvalidateAll, input logic SelFlush, + input logic VictimWay, input logic FlushWay, + input logic Invalidate, + output logic [LINELEN-1:0] ReadDataLineWay, - output logic WayHit, + output logic HitWay, output logic VictimDirtyWay, output logic [TAGLEN-1:0] VictimTagWay); @@ -91,7 +92,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign VictimDirtyWay = SelTag & Dirty & Valid; - assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); + assign HitWay = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); ///////////////////////////////////////////////////////////////////////////////////////////// // Data Array @@ -107,7 +108,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, end // AND portion of distributed read multiplexers - mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData); + mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData); assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux. ///////////////////////////////////////////////////////////////////////////////////////////// @@ -115,7 +116,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset | InvalidateAll) ValidBits <= #1 '0; + if (reset | Invalidate) ValidBits <= #1 '0; else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; end From e852cb8a31ffa3363757faf5743f12cc48d3a904 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Feb 2022 15:53:01 -0600 Subject: [PATCH 12/12] Eliminated more ports in cacheway. --- pipelined/src/cache/cache.sv | 5 +---- pipelined/src/cache/cacheway.sv | 6 ++---- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index a0e719b6..52d543a3 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -99,7 +99,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic ResetOrFlushAdr, ResetOrFlushWay; logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; - logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -113,7 +112,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .RAdr, .PAdr, .WriteWordWayEn, .WriteLineWayEn, .CacheWriteData, + .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Invalidate(InvalidateCacheM)); @@ -171,8 +170,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( assign ClearValidWay = ClearValid ? SelectedWay : '0; assign SetDirtyWay = SetDirty ? SelectedWay : '0; assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; - assign WriteWordWayEn = SetDirty ? SelectedWay : '0; - assign WriteLineWayEn = SetValid ? SelectedWay : '0; ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 2855f3fa..d9dfdfff 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -37,8 +37,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, - input logic WriteWordWayEn, - input logic WriteLineWayEn, input logic [LINELEN-1:0] CacheWriteData, input logic SetValidWay, input logic ClearValidWay, @@ -78,7 +76,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, onehotdecoder #(LOGWPL) adrdec( .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. - assign SelectedWriteWordEn = WriteLineWayEn ? '1 : WriteWordWayEn ? MemPAdrDecoded : '0; // OR-AND + assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array @@ -86,7 +84,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .Adr(RAdr), .ReadData(ReadTag), - .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn)); + .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); // AND portion of distributed tag multiplexer mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);