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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-01-04 18:41:52 -06:00
commit 0dd61a57da
5 changed files with 9 additions and 17 deletions
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2
pipelined/regression/Makefile
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@ -9,5 +9,7 @@ make all:
make -C ../../tests/wally-riscv-arch-test/ XLEN=32 make -C ../../tests/wally-riscv-arch-test/ XLEN=32
exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
# *** add optional imperas tests
# Link Linux test vectors (fix this later***) # Link Linux test vectors (fix this later***)
#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh

4
pipelined/regression/regression-wally.py
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@ -51,7 +51,7 @@ tc = TestCase(
grepstr="400100000 instructions") grepstr="400100000 instructions")
configs.append(tc) configs.append(tc)
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a", "imperas64c", "wally64priv", "imperas64mmu"] # "wally64i", #, "testsBP64"] tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
for test in tests64gc: for test in tests64gc:
tc = TestCase( tc = TestCase(
name=test, name=test,
@ -59,7 +59,7 @@ for test in tests64gc:
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!", cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a", "imperas32c", "wally32priv", "imperas32mmu"] #"wally32i", tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a", "imperas32c", "wally32priv"] #, "imperas32mmu""wally32i",
for test in tests32gc: for test in tests32gc:
tc = TestCase( tc = TestCase(
name=test, name=test,

10
pipelined/testbench/common/logging.sv
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@ -1,10 +0,0 @@
module logging(
input logic clk, reset,
input logic [31:0] HADDR,
input logic [1:0] HTRANS);
always @(posedge clk)
if (HTRANS != 2'b00 & HADDR == 0)
$display("%t Warning: access to memory address 0\n", $realtime);
endmodule

5
pipelined/testbench/testbench.sv
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@ -71,7 +71,6 @@ logic [3:0] dummy;
// check assertions for a legal configuration // check assertions for a legal configuration
riscvassertions riscvassertions(); riscvassertions riscvassertions();
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
// pick tests based on modes supported // pick tests based on modes supported
initial begin initial begin
@ -88,7 +87,7 @@ logic [3:0] dummy;
"arch64d": if (`D_SUPPORTED) tests = arch64d; "arch64d": if (`D_SUPPORTED) tests = arch64d;
"imperas64i": tests = imperas64i; "imperas64i": tests = imperas64i;
"imperas64p": tests = imperas64p; "imperas64p": tests = imperas64p;
"imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu; // "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64d": if (`D_SUPPORTED) tests = imperas64d;
"imperas64m": if (`M_SUPPORTED) tests = imperas64m; "imperas64m": if (`M_SUPPORTED) tests = imperas64m;
@ -111,7 +110,7 @@ logic [3:0] dummy;
"arch32f": if (`F_SUPPORTED) tests = arch32f; "arch32f": if (`F_SUPPORTED) tests = arch32f;
"imperas32i": tests = imperas32i; "imperas32i": tests = imperas32i;
"imperas32p": tests = imperas32p; "imperas32p": tests = imperas32p;
"imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; // "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m; "imperas32m": if (`M_SUPPORTED) tests = imperas32m;
"imperas32a": if (`A_SUPPORTED) tests = imperas32a; "imperas32a": if (`A_SUPPORTED) tests = imperas32a;

5
pipelined/testbench/tests.vh
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@ -36,6 +36,7 @@ string tvpaths[] = '{
"../../tests/imperas-riscv-tests/work/" "../../tests/imperas-riscv-tests/work/"
}; };
// *** make sure these are somewhere
string imperas64a[] = '{ string imperas64a[] = '{
`MYIMPERASTEST, `MYIMPERASTEST,
"rv64a/WALLY-AMO", "2110", "rv64a/WALLY-AMO", "2110",
@ -48,7 +49,7 @@ string tvpaths[] = '{
"rv32a/WALLY-LRSC", "2110" "rv32a/WALLY-LRSC", "2110"
}; };
string imperas32mmu[] = '{ /* string imperas32mmu[] = '{
`MYIMPERASTEST, `MYIMPERASTEST,
"rv32mmu/WALLY-MMU-SV32", "3000", "rv32mmu/WALLY-MMU-SV32", "3000",
"rv32mmu/WALLY-PMP", "3000" "rv32mmu/WALLY-PMP", "3000"
@ -61,7 +62,7 @@ string tvpaths[] = '{
"rv64mmu/WALLY-MMU-SV39", "3000", "rv64mmu/WALLY-MMU-SV39", "3000",
"rv64mmu/WALLY-PMP", "3000" "rv64mmu/WALLY-PMP", "3000"
//"rv64mmu/WALLY-PMA", "3000" //"rv64mmu/WALLY-PMA", "3000"
}; }; */
// *** restore CSR tests from Imperas old // *** restore CSR tests from Imperas old