From 08e6a104808e09075e92ecd231349120d888b56d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 4 Jan 2022 23:14:53 +0000
Subject: [PATCH] Removed imperas mmu tests; using wallypriv instead

---
 pipelined/regression/Makefile            |  2 ++
 pipelined/regression/regression-wally.py |  4 ++--
 pipelined/testbench/common/logging.sv    | 10 ----------
 pipelined/testbench/testbench.sv         |  5 ++---
 pipelined/testbench/tests.vh             |  5 +++--
 5 files changed, 9 insertions(+), 17 deletions(-)
 delete mode 100644 pipelined/testbench/common/logging.sv

diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile
index 1b327919..62ef4a4e 100644
--- a/pipelined/regression/Makefile
+++ b/pipelined/regression/Makefile
@@ -9,5 +9,7 @@ make all:
 	make -C ../../tests/wally-riscv-arch-test/ XLEN=32 
 	exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
 
+	# *** add optional imperas tests
+
 	# Link Linux test vectors (fix this later***)
 	#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
diff --git a/pipelined/regression/regression-wally.py b/pipelined/regression/regression-wally.py
index 5d503498..d740784d 100755
--- a/pipelined/regression/regression-wally.py
+++ b/pipelined/regression/regression-wally.py
@@ -51,7 +51,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 configs.append(tc)
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a",  "imperas64c", "wally64priv", "imperas64mmu"] # "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a",  "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,
@@ -59,7 +59,7 @@ for test in tests64gc:
         cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
-tests32gc = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a",  "imperas32c", "wally32priv", "imperas32mmu"]  #"wally32i", 
+tests32gc = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a",  "imperas32c", "wally32priv"]  #, "imperas32mmu""wally32i", 
 for test in tests32gc:
   tc = TestCase(
         name=test,
diff --git a/pipelined/testbench/common/logging.sv b/pipelined/testbench/common/logging.sv
deleted file mode 100644
index f37f6340..00000000
--- a/pipelined/testbench/common/logging.sv
+++ /dev/null
@@ -1,10 +0,0 @@
-module logging(
-  input logic clk, reset,
-  input logic [31:0] HADDR,
-  input logic [1:0]  HTRANS);
-
-  always @(posedge clk)
-    if (HTRANS != 2'b00 & HADDR == 0)
-      $display("%t Warning: access to memory address 0\n", $realtime);
-endmodule
-
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 09e06059..bbb0df15 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -71,7 +71,6 @@ logic [3:0] dummy;
 
   // check assertions for a legal configuration
   riscvassertions riscvassertions();
-  logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
 
   // pick tests based on modes supported
   initial begin
@@ -88,7 +87,7 @@ logic [3:0] dummy;
         "arch64d":      if (`D_SUPPORTED) tests = arch64d;
         "imperas64i":                     tests = imperas64i;
         "imperas64p":                     tests = imperas64p;
-        "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
+//        "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
         "imperas64f":   if (`F_SUPPORTED) tests = imperas64f;
         "imperas64d":   if (`D_SUPPORTED) tests = imperas64d;
         "imperas64m":   if (`M_SUPPORTED) tests = imperas64m;
@@ -111,7 +110,7 @@ logic [3:0] dummy;
         "arch32f":      if (`F_SUPPORTED) tests = arch32f;
         "imperas32i":                     tests = imperas32i;
         "imperas32p":                     tests = imperas32p;
-        "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
+//        "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
         "imperas32f":   if (`F_SUPPORTED) tests = imperas32f;
         "imperas32m":   if (`M_SUPPORTED) tests = imperas32m;
         "imperas32a":   if (`A_SUPPORTED) tests = imperas32a;
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index c4484c8c..672aedbc 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -36,6 +36,7 @@ string tvpaths[] = '{
     "../../tests/imperas-riscv-tests/work/"
 };
 
+  // *** make sure these are somewhere
   string imperas64a[] = '{
     `MYIMPERASTEST,
     "rv64a/WALLY-AMO", "2110",
@@ -48,7 +49,7 @@ string tvpaths[] = '{
     "rv32a/WALLY-LRSC", "2110"
   };
 
-  string imperas32mmu[] = '{
+/*  string imperas32mmu[] = '{
     `MYIMPERASTEST, 
     "rv32mmu/WALLY-MMU-SV32", "3000",
     "rv32mmu/WALLY-PMP", "3000"
@@ -61,7 +62,7 @@ string tvpaths[] = '{
     "rv64mmu/WALLY-MMU-SV39", "3000",
     "rv64mmu/WALLY-PMP", "3000"
     //"rv64mmu/WALLY-PMA", "3000"
-  };
+  }; */
 
   // *** restore CSR tests from Imperas old