forked from Github_Repos/cvw
72 lines
2.6 KiB
Systemverilog
72 lines
2.6 KiB
Systemverilog
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///////////////////////////////////////////
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// block ram model should be equivalent to srsam.
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//
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// Written: Ross Thompson
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// March 29, 2022
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// Modified: Based on UG901 vivado documentation.
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//
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// Purpose: On-chip SIMPLERAM, external to core
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// This model actually works correctly with vivado.
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`include "wally-config.vh"
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module bram1p1rw
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#(
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//--------------------------------------------------------------------------
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parameter NUM_COL = 8,
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parameter COL_WIDTH = 8,
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parameter ADDR_WIDTH = 10,
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// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
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parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
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//----------------------------------------------------------------------
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) (
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input logic clk,
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input logic ena,
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input logic [NUM_COL-1:0] we,
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input logic [ADDR_WIDTH-1:0] addr,
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output logic [DATA_WIDTH-1:0] dout,
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input logic [DATA_WIDTH-1:0] din
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);
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// Core Memory
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logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
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integer i;
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initial begin
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$readmemh("big64.txt", RAM);
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end
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always @ (posedge clk) begin
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dout <= RAM[addr];
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if(ena) begin
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for(i=0;i<NUM_COL;i=i+1) begin
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if(we[i]) begin
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RAM[addr][i*COL_WIDTH +: COL_WIDTH] <= din[i*COL_WIDTH +:COL_WIDTH];
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end
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end
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end
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end
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endmodule // bytewrite_tdp_ram_rf
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