cvw/pipelined/src
2022-05-18 17:01:55 +00:00
..
cache Removing unused signals 2022-05-12 14:36:15 +00:00
ebu Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
fma filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
fpu More signal cleanup 2022-05-12 15:39:44 +00:00
generic Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
hazard Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
ieu More signal cleanup 2022-05-12 15:39:44 +00:00
ifu Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
lsu More unused signal cleanup 2022-05-12 15:21:09 +00:00
mmu Clean up unused signals 2022-05-12 14:49:58 +00:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
privileged Cause simplification 2022-05-12 23:47:21 +00:00
uncore Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
wally More unused signal cleanup 2022-05-12 15:26:08 +00:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00