Ross Thompson 91e99f0d34 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-04-04 10:56:10 -05:00
..
bram1p1rw.sv	Partial cleanup of memories.	2022-03-30 11:09:21 -05:00
bram2p1r1w.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
flop.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
flopen.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
flopenl.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
flopenr.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
flopenrc.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
flopens.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
flopr.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
floprc.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
simpleram.sv	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
synchronizer.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00