2021-05-24 13:28:16 +00:00
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///////////////////////////////////////////
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2022-09-20 10:57:57 +00:00
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// fpu.sv
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2021-05-24 13:28:16 +00:00
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//
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2023-01-11 19:06:37 +00:00
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// Written: me@KatherineParry.com, James Stine, Brett Mathis, David Harris
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2021-06-23 20:42:40 +00:00
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// Modified: 6/23/2021
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2021-05-24 13:28:16 +00:00
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//
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2023-01-11 19:06:37 +00:00
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// Purpose: Floating Point Unit Top-Level Interface
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2021-05-24 13:28:16 +00:00
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//
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2023-01-12 12:35:44 +00:00
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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2023-01-11 23:15:08 +00:00
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// A component of the CORE-V-WALLY configurable RISC-V project.
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2021-05-24 13:28:16 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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2021-05-24 13:28:16 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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2021-05-24 13:28:16 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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2021-05-24 13:28:16 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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2022-01-07 12:58:40 +00:00
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////////////////////////////////////////////////////////////////////////////////////////////////
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2021-04-08 18:03:21 +00:00
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`include "wally-config.vh"
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2021-04-04 18:09:13 +00:00
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module fpu (
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2023-01-16 02:23:09 +00:00
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input logic clk,
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input logic reset,
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// Hazards
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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output logic FPUStallD, // Stall the decode stage (To HZU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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// CSRs
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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// Decode stage
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input logic [31:0] InstrD, // instruction (from IFU)
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// Execute stage
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input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations
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input logic IntDivE, W64E, // Integer division on FPU
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
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input logic [4:0] RdE, // which FP register to write to (from IEU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic FCvtIntE, // Convert to int (to IEU)
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// Memory stage
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input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations
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input logic [4:0] RdM, // which FP register to write to (from IEU)
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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2023-02-21 17:32:17 +00:00
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
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2023-01-16 02:23:09 +00:00
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output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
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// Writeback stage
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input logic [4:0] RdW, // which FP register to write to (from IEU)
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input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU)
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output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic [`XLEN-1:0] FIntDivResultW // Result from integer division (to IEU)
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2023-01-11 20:18:06 +00:00
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);
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2021-07-24 18:59:57 +00:00
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2023-01-16 02:23:09 +00:00
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// RISC-V FPU specifics:
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// - multiprecision support uses NAN-boxing, putting 1's in unused msbs
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// - RISC-V detects underflow after rounding
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// control signals
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input
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logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input
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logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation
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logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation
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logic FRegWriteE; // Write floating-point register
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// regfile signals
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logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
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logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding)
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logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
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logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
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// unpacking signals
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logic XsE, YsE, ZsE; // input's sign - execute stage
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logic XsM, YsM; // input's sign - memory stage
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logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
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logic [`NE-1:0] ZeM; // input's exponent - memory stage
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logic [`NF:0] XmE, YmE, ZmE; // input's significand - execute stage
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logic [`NF:0] XmM, YmM, ZmM; // input's significand - memory stage
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XSubnormE; // is the input subnormal
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM; // is the input zero - memory stage
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XExpMaxE; // is the exponent all ones (max value)
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2023-02-18 04:51:43 +00:00
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logic [`FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations
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2023-01-16 02:23:09 +00:00
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// Fma Signals
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logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting
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logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying
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logic [3*`NF+3:0] SmE, SmM; // Sum significand
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logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
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logic [`NE+1:0] SeE,SeM; // Sum exponent
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logic InvAE, InvAM; // Invert addend
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logic AsE, AsM; // Addend sign
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logic PsE, PsM; // Product sign
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logic SsE, SsM; // Sum sign
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logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count
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// Cvt Signals
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logic [`NE:0] CeE, CeM; // convert intermediate expoent
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by
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logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
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logic CsE, CsM; // convert result sign
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logic IntZeroE, IntZeroM; // is the integer zero?
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logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
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logic [`XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU)
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// divide signals
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logic [`DIVb:0] QmM; // fdivsqrt signifcand
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logic [`NE+1:0] QeM; // fdivsqrt exponent
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logic DivStickyM; // fdivsqrt sticky bit
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logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
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logic [`XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU)
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// result and flag signals
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logic [`XLEN-1:0] ClassResE; // classify result
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logic [`FLEN-1:0] CmpFpResE; // compare result to FPU (min/max)
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logic [`XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le)
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logic CmpNVE; // compare invalid flag (Not Valid)
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logic [`FLEN-1:0] SgnResE; // sign injection result
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logic [`XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move)
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logic [`FLEN-1:0] PostProcResM; // Postprocessor output
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logic [4:0] PostProcFlgM; // Postprocessor flags
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logic PreNVE, PreNVM; // selected flag that is ready in the memory stage
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logic [`FLEN-1:0] FpResM, FpResW; // FPU preliminary result
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logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage
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logic [`FLEN-1:0] FResultW; // final FP result being written to the FP register
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// other signals
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logic [`FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv
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logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
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logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
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//////////////////////////////////////////////////////////////////////////////////////////
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// Decode Stage: fctrl decoder, read register file
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//////////////////////////////////////////////////////////////////////////////////////////
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// calculate FP control signals
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fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
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.Funct3E, .IntDivE, .InstrD,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
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.reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
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.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
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2023-02-21 17:32:17 +00:00
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.IllegalFPUInstrD, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
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2023-01-16 02:23:09 +00:00
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.FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW,
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.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
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// FP register file
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fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
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.a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]),
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.a4(RdW), .wd4(FResultW),
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.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));
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// D/E pipeline registers
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flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
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flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
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flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
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//////////////////////////////////////////////////////////////////////////////////////////
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// Execute Stage: hazards, forwarding, unpacking, execution units
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//////////////////////////////////////////////////////////////////////////////////////////
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// Hazard unit for FPU: determines if any forwarding or stalls are needed
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fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E,
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.FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM,
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.XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
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// forwarding muxs
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mux3 #(`FLEN) fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE);
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mux3 #(`FLEN) fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE);
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mux3 #(`FLEN) fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE);
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// Select NAN-boxed value of Y = 1.0 in proper format for fma to add/subtract X*Y+Z
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2023-02-18 04:51:43 +00:00
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if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)};
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else if(`FPSIZES == 2)
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mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
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else if(`FPSIZES == 3 | `FPSIZES == 4)
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mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)},
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{{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)},
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{{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)},
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{2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
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2023-01-16 02:23:09 +00:00
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assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
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mux2 #(`FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
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// Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
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// For add and subtract, Z comes from second source operand
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2023-02-18 04:51:43 +00:00
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if(`FPSIZES == 1) assign BoxedZeroE = 0;
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2023-01-16 02:23:09 +00:00
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else if(`FPSIZES == 2)
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mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
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else if(`FPSIZES == 3 | `FPSIZES == 4)
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mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}},
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{{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}},
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{{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}},
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(`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
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assign FmaZSelE = {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]};
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mux3 #(`FLEN) fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE);
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// unpack unit: splits FP inputs into their parts and classifies SNaN, NaN, Subnorm, Norm, Zero, Infifnity
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unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE),
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.Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
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.XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE),
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.YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE),
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.XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE),
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2023-02-18 04:51:43 +00:00
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.ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE), .XPostBox(XPostBoxE));
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2023-01-16 02:23:09 +00:00
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// fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub
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fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE),
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.XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE),
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.As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), .ASticky(FmaAStickyE));
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// divide and square root: fdiv, fsqrt, optionally integer division
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
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.StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
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.QmM, .FIntDivResultM);
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// compare: fmin/fmax, flt/fle/feq
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fcmp fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE),
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.Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE),
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.XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE),
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.CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE));
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// sign injection: fsgnj/fsgnjx/fsgnjn
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2023-02-18 04:51:43 +00:00
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fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XPostBoxE), .Fmt(FmtE), .SgnRes(SgnResE));
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2023-01-16 02:23:09 +00:00
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// classify: fclass
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fclassify fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE),
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.XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE));
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// convert: fcvt.*.*
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fcvt fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE),
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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// NaN Box SrcA to convert integer to requested FP size
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if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE};
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else if(`FPSIZES == 2)
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mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
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else if(`FPSIZES == 3 | `FPSIZES == 4)
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mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ForwardedSrcAE[`S_LEN-1:0]},
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{{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]},
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{{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]},
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{{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
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// select a result that may be written to the FP register
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mux3 #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
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assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
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// select the result that may be written to the integer register - to IEU
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if(`FPSIZES == 1)
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assign SgnExtXE = XE;
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else if(`FPSIZES == 2)
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mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
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else if(`FPSIZES == 3 | `FPSIZES == 4)
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mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]},
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{{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]},
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{{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]},
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XE, FmtE, SgnExtXE);
|
2023-02-18 04:51:43 +00:00
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|
2023-01-16 02:23:09 +00:00
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if (`FLEN>`XLEN)
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assign IntSrcXE = SgnExtXE[`XLEN-1:0];
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else
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assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
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mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
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// E/M pipe registers
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// Need to stall during divsqrt iterations to avoid capturing bad flags from stale forwarded sources
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|
|
assign StallUnpackedM = StallM | (FDivBusyE & ~IFDivStartE | FDivDoneE);
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|
flopenrc #(`NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
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flopenrc #(`NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
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flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
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flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
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flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
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|
flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM,
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|
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|
|
{XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
|
|
|
|
|
{XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
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flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);
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flopenrc #(3*`NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
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|
|
|
flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
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|
|
|
|
{FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
|
|
|
|
|
{FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
|
|
|
|
|
flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,
|
|
|
|
|
{CeE, CvtShiftAmtE, CvtResSubnormUfE, CsE, IntZeroE, CvtLzcInE},
|
|
|
|
|
{CeM, CvtShiftAmtM, CvtResSubnormUfM, CsM, IntZeroM, CvtLzcInM});
|
|
|
|
|
flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
|
|
|
|
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
// Memory Stage: postprocessor and result muxes
|
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
|
|
postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM),
|
|
|
|
|
.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
|
|
|
|
|
.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM),
|
|
|
|
|
.FmaSm(SmM), .DivQe(QeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
|
|
|
|
|
.CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM),
|
|
|
|
|
.ToInt(FWriteIntM), .DivSticky(DivStickyM), .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM),
|
|
|
|
|
.PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
|
|
|
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|
|
|
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|
|
// FPU flag selection - to privileged
|
|
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|
|
mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
|
|
|
|
|
mux2 #(`FLEN) FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
|
|
|
|
|
|
|
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|
|
// M/W pipe registers
|
|
|
|
|
flopenrc #(`FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW);
|
|
|
|
|
flopenrc #(`XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW);
|
|
|
|
|
flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW);
|
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|
|
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
// Writeback Stage: result mux
|
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
|
|
// select the result to be written to the FP register
|
|
|
|
|
mux2 #(`FLEN) FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW);
|
2022-06-13 22:47:51 +00:00
|
|
|
|
2021-06-01 19:45:32 +00:00
|
|
|
endmodule // fpu
|
