2021-07-02 16:53:05 +00:00
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2022-07-07 23:01:33 +00:00
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///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: Comparison unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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2022-07-20 02:27:39 +00:00
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2021-07-02 16:53:05 +00:00
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`include "wally-config.vh"
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// OpCtrl values
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// 110 min
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// 101 max
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// 010 equal
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// 001 less than
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// 011 less than or equal
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2022-01-01 23:50:23 +00:00
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module fcmp (
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input logic [`FMTBITS-1:0] Fmt, // format of fp number
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input logic [2:0] OpCtrl, // see above table
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input logic Xs, Ys, // input signs
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input logic [`NE-1:0] Xe, Ye, // input exponents
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input logic [`NF:0] Xm, Ym, // input mantissa
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input logic XZero, YZero, // is zero
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input logic XNaN, YNaN, // is NaN
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input logic XSNaN, YSNaN, // is signaling NaN
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input logic [`FLEN-1:0] X, Y, // original inputs (before unpacker)
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output logic CmpNV, // invalid flag
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output logic [`FLEN-1:0] CmpFpRes, // compare floating-point result
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output logic [`XLEN-1:0] CmpIntRes // compare integer result
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);
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logic LTabs, LT, EQ; // is X < or > or = Y
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logic [`FLEN-1:0] NaNRes; // NaN result
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logic BothZero; // are both inputs zero
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logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
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assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
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assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
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assign EQ = (X == Y);
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assign BothZero = XZero&YZero;
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assign EitherNaN = XNaN|YNaN;
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assign EitherSNaN = XSNaN|YSNaN;
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// flags
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// Min/Max - if an input is a signaling NaN set invalid flag
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// LT/LE - signaling - sets invalid if NaN input
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// EQ - quiet - sets invalid if signaling NaN input
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always_comb begin
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case (OpCtrl[2:0])
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3'b110: CmpNV = EitherSNaN;//min
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3'b101: CmpNV = EitherSNaN;//max
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3'b010: CmpNV = EitherSNaN;//equal
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3'b001: CmpNV = EitherNaN;//less than
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3'b011: CmpNV = EitherNaN;//less than or equal
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default: CmpNV = 1'bx;
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endcase
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end
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// fmin/fmax of two NaNs returns a quiet NaN of the appropriate size
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// for IEEE, return the payload of X
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// for RISC-V, return the canonical NaN
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// select the NaN result
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if (`FPSIZES == 1)
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if(`IEEE754) assign NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
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else assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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else if (`FPSIZES == 2)
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if(`IEEE754) assign NaNRes = Fmt ? {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
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else assign NaNRes = Fmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
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else if (`FPSIZES == 3)
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always_comb
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case (Fmt)
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`FMT:
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if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
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else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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`FMT1:
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if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
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else NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
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`FMT2:
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if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, Xs, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
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else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
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default: NaNRes = {`FLEN{1'bx}};
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endcase
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else if (`FPSIZES == 4)
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always_comb
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case (Fmt)
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2'h3:
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if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
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else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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2'h1:
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if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, Xs, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
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else NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
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2'h0:
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if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, Xs, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
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else NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
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2'h2:
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if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, Xs, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
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else NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
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endcase
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// Min/Max
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// - outputs the min/max of X and Y
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// - -0 < 0
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// - if both are NaN return quiet X
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// - if one is a NaN output the non-NaN
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always_comb
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if(OpCtrl[0]) // MAX
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if(XNaN)
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if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN
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else CmpFpRes = Y; // X = NaN Y != NaN
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else
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if(YNaN) CmpFpRes = X; // X != NaN Y = NaN
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else // X,Y != NaN
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if(LT) CmpFpRes = Y; // X < Y
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else CmpFpRes = X; // X > Y
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else // MIN
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if(XNaN)
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if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN
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else CmpFpRes = Y; // X = NaN Y != NaN
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else
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if(YNaN) CmpFpRes = X; // X != NaN Y = NaN
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else // X,Y != NaN
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if(LT) CmpFpRes = X; // X < Y
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else CmpFpRes = Y; // X > Y
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// LT/LE/EQ
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// - -0 = 0
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// - inf = inf and -inf = -inf
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// - return 0 if comparison with NaN (unordered)
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assign CmpIntRes = {(`XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
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endmodule
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