| .. |
|
debug
|
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
|
2022-10-24 15:38:39 -05:00 |
|
bootrom.txt
|
Added bootrom.txt.
|
2022-03-30 17:29:48 -05:00 |
|
insert_debug_comment.sh
|
Updated fpga constraints.
|
2023-01-20 20:16:33 -06:00 |
|
Makefile
|
At least it simulates and gets through fpga elaboration.
|
2023-07-21 18:40:26 -05:00 |
|
probe
|
Added Jacob's ILA script.
|
2023-04-06 15:32:36 -05:00 |
|
wally.tcl
|
Removed all old references to the old flash card controller.
|
2023-07-24 15:45:57 -05:00 |
|
wave_config.wcfg
|
Updated fpga wave config.
|
2023-06-19 12:28:30 -05:00 |
|
xlnx_ahblite_axi_bridge.tcl
|
Added more support for Arty A7 board.
|
2023-04-10 16:01:17 -05:00 |
|
xlnx_axi_clock_converter.tcl
|
Added more support for Arty A7 board.
|
2023-04-10 16:01:17 -05:00 |
|
xlnx_axi_crossbar.tcl
|
The Vivado-RISC-V SDC works. Wally is now booting through it.
|
2023-05-26 15:42:33 -05:00 |
|
xlnx_axi_dwidth_conv_32to64.tcl
|
Connected the axi_sdc_controller with an axi crossbar.
|
2023-01-13 13:56:01 -06:00 |
|
xlnx_axi_dwidth_conv_64to32.tcl
|
Connected the axi_sdc_controller with an axi crossbar.
|
2023-01-13 13:56:01 -06:00 |
|
xlnx_axi_dwidth_converter.tcl
|
Connected the axi_sdc_controller with an axi crossbar.
|
2023-01-13 13:56:01 -06:00 |
|
xlnx_axi_prtcl_conv.tcl
|
Modified makefile. Added axi protocol converter IP.
|
2023-01-23 19:30:29 -06:00 |
|
xlnx_ddr3-artya7-mig.prj
|
It's almost working.
|
2023-04-18 14:24:59 -05:00 |
|
xlnx_ddr3-ArtyA7.tcl
|
Finally fixed the ddr3 mig script to work correclty.
|
2023-04-14 11:41:51 -05:00 |
|
xlnx_ddr4-vcu108.tcl
|
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
|
2022-10-24 15:38:39 -05:00 |
|
xlnx_ddr4-vcu118.tcl
|
Updated vcu118 constraints to run cpu at 38.43Mhz.
|
2022-11-15 10:19:38 -06:00 |
|
xlnx_ddr4.tcl
|
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
|
2022-10-24 15:38:39 -05:00 |
|
xlnx_mmcm.tcl
|
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
|
2023-07-24 10:46:49 -05:00 |
|
xlnx_proc_sys_reset.tcl
|
Added more support for Arty A7 board.
|
2023-04-10 16:01:17 -05:00 |
b1f7a5768f