David Harris d3ce683e06 Removed other unused signals from Verilog		2023-11-20 23:37:56 -08:00
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fdivsqrt.sv	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
fdivsqrtcycles.sv	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
fdivsqrtexpcalc.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
fdivsqrtfgen2.sv	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
fdivsqrtfgen4.sv	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
fdivsqrtfsm.sv	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
fdivsqrtiter.sv	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
fdivsqrtpostproc.sv	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:27 -08:00
fdivsqrtpreproc.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
fdivsqrtstage2.sv	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
fdivsqrtstage4.sv	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
fdivsqrtuotfc2.sv	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
fdivsqrtuotfc4.sv	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
fdivsqrtuslc2.sv	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
fdivsqrtuslc4.sv	Divider cleanup	2023-11-12 19:41:12 -08:00
fdivsqrtuslc4cmp.sv	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00