cvw/fpga/generator
2024-01-31 13:19:28 -06:00
..
debug
bootrom.txt
insert_debug_comment.sh Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Makefile Update the fpga scripts to use the new derivative configs. 2024-01-31 13:19:28 -06:00
probe
wally.tcl Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
wave_config.wcfg Updateds to vcu118 constraints and device tree. 2023-08-02 16:51:32 -05:00
xlnx_ahblite_axi_bridge.tcl
xlnx_axi_clock_converter.tcl
xlnx_axi_crossbar.tcl
xlnx_axi_dwidth_conv_32to64.tcl
xlnx_axi_dwidth_conv_64to32.tcl
xlnx_axi_dwidth_converter.tcl
xlnx_axi_prtcl_conv.tcl
xlnx_ddr3-artya7-mig.prj
xlnx_ddr3-ArtyA7.tcl
xlnx_ddr4-vcu108.tcl
xlnx_ddr4-vcu118.tcl Pushed vcu118 to 71MHz. 2023-08-25 17:04:50 -05:00
xlnx_ddr4.tcl
xlnx_mmcm.tcl Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. 2023-11-13 16:44:02 -06:00
xlnx_proc_sys_reset.tcl