Rose Thompson b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.		2024-07-24 12:47:50 -05:00
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csrindextoaddr.sv	Resolved more lint errors in the rvvi synthesized hardware.	2024-07-23 12:23:04 -05:00
packetizer.sv	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00
priorityaomux.sv	Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.	2024-07-23 13:18:03 -05:00
regchangedetect.sv	Moved all rvvi files to rvvi directory.	2024-07-23 13:03:21 -05:00
rvvisynth.sv	Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.	2024-07-23 17:44:37 -05:00
triggergen.sv	Yay. It's actually working! The FPGA/ImperasDV hybrid is working.	2024-07-10 15:10:37 -05:00