| .. | 
		
		
			
			
			
			
				| debug | Setup to run with both the vcu108 and vcu118 boards.  Set the parameters in the Makefile. | 2022-10-24 15:38:39 -05:00 | 
		
			
			
			
			
				| bootrom.txt | Added bootrom.txt. | 2022-03-30 17:29:48 -05:00 | 
		
			
			
			
			
				| insert_debug_comment.sh | Added Wally github address to header comments | 2024-01-29 05:38:11 -08:00 | 
		
			
			
			
			
				| Makefile | Get's the fpga building again after the git history rewrite. | 2023-12-14 17:08:25 -06:00 | 
		
			
			
			
			
				| probe | Added Jacob's ILA script. | 2023-04-06 15:32:36 -05:00 | 
		
			
			
			
			
				| wally.tcl | Replaced fpga's verilog top with system verilog. | 2023-12-15 13:42:52 -06:00 | 
		
			
			
			
			
				| wave_config.wcfg | Updateds to vcu118 constraints and device tree. | 2023-08-02 16:51:32 -05:00 | 
		
			
			
			
			
				| xlnx_ahblite_axi_bridge.tcl | Added more support for Arty A7 board. | 2023-04-10 16:01:17 -05:00 | 
		
			
			
			
			
				| xlnx_axi_clock_converter.tcl | Added more support for Arty A7 board. | 2023-04-10 16:01:17 -05:00 | 
		
			
			
			
			
				| xlnx_axi_crossbar.tcl | The Vivado-RISC-V SDC works. Wally is now booting through it. | 2023-05-26 15:42:33 -05:00 | 
		
			
			
			
			
				| xlnx_axi_dwidth_conv_32to64.tcl | Connected the axi_sdc_controller with an axi crossbar. | 2023-01-13 13:56:01 -06:00 | 
		
			
			
			
			
				| xlnx_axi_dwidth_conv_64to32.tcl | Connected the axi_sdc_controller with an axi crossbar. | 2023-01-13 13:56:01 -06:00 | 
		
			
			
			
			
				| xlnx_axi_dwidth_converter.tcl | Connected the axi_sdc_controller with an axi crossbar. | 2023-01-13 13:56:01 -06:00 | 
		
			
			
			
			
				| xlnx_axi_prtcl_conv.tcl | Modified makefile. Added axi protocol converter IP. | 2023-01-23 19:30:29 -06:00 | 
		
			
			
			
			
				| xlnx_ddr3-artya7-mig.prj | It's almost working. | 2023-04-18 14:24:59 -05:00 | 
		
			
			
			
			
				| xlnx_ddr3-ArtyA7.tcl | Finally fixed the ddr3 mig script to work correclty. | 2023-04-14 11:41:51 -05:00 | 
		
			
			
			
			
				| xlnx_ddr4-vcu108.tcl | Setup to run with both the vcu108 and vcu118 boards.  Set the parameters in the Makefile. | 2022-10-24 15:38:39 -05:00 | 
		
			
			
			
			
				| xlnx_ddr4-vcu118.tcl | Pushed vcu118 to 71MHz. | 2023-08-25 17:04:50 -05:00 | 
		
			
			
			
			
				| xlnx_ddr4.tcl | Setup to run with both the vcu108 and vcu118 boards.  Set the parameters in the Makefile. | 2022-10-24 15:38:39 -05:00 | 
		
			
			
			
			
				| xlnx_mmcm.tcl | Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. | 2023-11-13 16:44:02 -06:00 | 
		
			
			
			
			
				| xlnx_proc_sys_reset.tcl | Added more support for Arty A7 board. | 2023-04-10 16:01:17 -05:00 |